MC100E210FN

更新时间： 2024-09-30 22:35:15

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟驱动器逻辑集成电路
页数	文件大小	规格书
6页	111K
描述
LOW VOLTAGE DUAL 1:4, 1:5 DIFFERENTIAL FANOUT BUFFER

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MC100E210FN 技术参数

生命周期：	Transferred	零件包装代码：	QLCC
包装说明：	QCCJ,	针数：	28
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.47	系列：	100E
输入调节：	DIFFERENTIAL	JESD-30 代码：	S-PQCC-J28
JESD-609代码：	e0	长度：	11.5062 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	功能数量：	2
反相输出次数：		端子数量：	28
实输出次数：	9	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	传播延迟（tpd）：	0.75 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.075 ns
座面最大高度：	4.57 mm	最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	4.75 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	ECL
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	11.5062 mm
Base Number Matches：	1

MC100E210FN 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC100LVE210 is a low voltage, low skew dual differential ECL

fanout buffer designed with clock distribution in mind. The device features

two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device

features fully differential clock paths to minimize both device and system

skew. The dual buffer allows for the fanout of two signals through a single

chip, thus reducing the skew between the two fundamental signals from a

part–to–part skew down to an output–to–output skew. This capability

reduces the skew by a factor of 4 as compared to using two LVE111’s to

accomplish the same task. The MC100LVE210 works from a –3.3V

supply while the MC100E210 provides identical function and

performance from a standard –4.5V 100E voltage supply.

LOW VOLTAGE

DUAL 1:4, 1:5 DIFFERENTIAL

FANOUT BUFFER

• Dual Differential Fanout Buffers

• 200ps Part–to–Part Skew

• 50ps Typical Output–to–Output Skew

• Low Voltage ECL/PECL Compatible

• 28–lead PLCC Packaging

For applications which require a single–ended input, the V

reference

voltage is supplied. For single–ended input applications the V

reference should be connected to the CLK input and bypassed to ground

FN SUFFIX

PLASTIC PACKAGE

CASE 776–02

via a 0.01µf capacitor. The input signal is then driven into the CLK input.

To ensure that the tight skew specification is met it is necessary that

both sides of the differential output are terminated into 50Ω, even if only

one side is being used. In most applications all nine differential pairs will

be used and therefore terminated. In the case where fewer than nine

pairs are used it is necessary to terminate at least the output pairs

adjacent to the output pair being used in order to maintain minimum skew.

Failure to follow this guideline will result in small degradations of

propagation delay (on the order of 10–20ps) of the outputs being used,

while not catastrophic to most designs this will result in an increase in

skew. Note that the package corners isolate outputs from one another

such that the guideline expressed above holds only for outputs on the

same side of the package.

The MC100LVE210, as with most ECL devices, can be operated from a positive V

supply in PECL mode. This allows the

LVE210 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE210’s

performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line

terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage

of V –2.0V will need to be provided. For more information on using PECL, designers should refer to Motorola Application Note

AN1406/D.

7/95

REV 1

4–1

Motorola, Inc. 1996

12 3 4 5 6

中文翻译

下载PDF

与MC100E210FN相关器件

型号	品牌	获取价格	描述	数据表
MC100E210FNG	ONSEMI	获取价格	5.0 V ECL Dual 1:4, 1:5 Differential Clock/Data Fanout Buffer, 28 LEAD PLCC, 37-TUBE
MC100E210FNR2	ONSEMI	获取价格	Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer
MC100E210FNR2	MOTOROLA	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, PLASTI
MC100E210FNR2G	ONSEMI	获取价格	暂无描述
MC100E211	ONSEMI	获取价格	1:6 DIFFERENTIAL CLOCK DISTRIBUTION CHIP
MC100E211FN	MOTOROLA	获取价格	1:6 DIFFERENTIAL CLOCK DISTRIBUTION CHIP
MC100E211FN	ONSEMI	获取价格	5V ECL 1:6 Differential Clock Distribution Chip
MC100E211FNG	ONSEMI	获取价格	5V ECL 1:6 Differential Clock Distribution Chip
MC100E211FNR2	ONSEMI	获取价格	5V ECL 1:6 Differential Clock Distribution Chip
MC100E211FNR2G	ONSEMI	获取价格	5V ECL 1:6 Differential Clock Distribution Chip

与MC100E210FN相关文章

塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

38
英特尔震撼发布：128核心256线程的至强6性能核处理器
2024-09-29

32
SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

28
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

40

产品中心

服务支持

精选活动

关于我们

帮助中心

MC100E210FN

MC100E210FN 技术参数

MC100E210FN 数据手册

与MC100E210FN相关器件

与MC100E210FN相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MC100E210FN

MC100E210FN 技术参数

MC100E210FN 数据手册

与MC100E210FN相关器件

与MC100E210FN相关文章

您还可以找

您在本页遇到什么问题？