Datasheet > MC100E196FNG

MC100E196FNG

更新时间： 2024-10-01 05:10:27

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描述
5V ECL Programmable Delay Chip

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MC100E196FNG 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QLCC
包装说明：	QCCJ, LDCC28,.5SQ	针数：	28
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
Factory Lead Time：	1 week	风险等级：	7.73
其他特性：	NECL MODE: VCC=0 WITH VEE=-4.2 V TO -5.7 V	系列：	100E
JESD-30 代码：	S-PQCC-J28	JESD-609代码：	e3
长度：	11.505 mm	逻辑集成电路类型：	ACTIVE DELAY LINE
功能数量：	1	抽头/阶步数：	127
端子数量：	28	最高工作温度：	85 °C
最低工作温度：		输出特性：	OPEN-EMITTER
输出极性：	COMPLEMENTARY	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC28,.5SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	260	电源：	-5.2 V
最大电源电流（ICC）：	156 mA	可编程延迟线：	YES
Prop。Delay @ Nom-Sup：	4.72 ns	认证状态：	Not Qualified
座面最大高度：	4.57 mm	子类别：	Delay Lines
最大供电电压 (Vsup)：	5.7 V	最小供电电压 (Vsup)：	4.2 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	ECL	温度等级：	OTHER
端子面层：	Tin (Sn)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	总延迟标称（td）：	3.63 ns
宽度：	11.505 mm	Base Number Matches：	1

MC100E196FNG 数据手册

MC10E196, MC100E196

5VꢀECL Programmable

Delay Chip

Description

The MC10E/100E196 is a programmable delay chip (PDC)

designed primarily for very accurate differential ECL input edge

placement applications.

http://onsemi.com

The delay section consists of a chain of gates and a linear ramp delay

adjust organized as shown in the logic symbol. The first two delay

elements feature gates that have been modified to have delays

1.25 and 1.5 times the basic gate delay of approximately 80 ps. These

two elements provide the E196 with a digitally-selectable resolution

of approximately 20 ps. The required device delay is selected by the

seven address inputs D[0:6], which are latched on chip by a high signal

on the latch enable (LEN) control.

PLCC−28

FN SUFFIX

CASE 776

MARKING DIAGRAM*

The FTUNE input takes an analog voltage and applies it to an

internal linear ramp for reducing the 20 ps Least Significant Bit (LSB)

minimum resolution still further. The FTUNE input is what

differentiates the E196 from the E195.

MCxxxE196FNG

AWLYYWW

An eighth latched input, D7, is provided for cascading multiple

PDC’s for increased programmable range. The cascade logic allows

full control of multiple PDC’s, at the expense of only a single added

line to the data bus for each additional PDC, without the need for any

external gating.

xxx

= 10 or 100

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

The V pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

differential input is connected to V as a switching reference voltage.

may also rebias AC coupled inputs. When used, decouple V

and V via a 0.01 mF capacitor and limit current sourcing or sinking

*For additional marking information, refer to

Application Note AND8002/D.

to 0.5 mA. When not used, V should be left open.

The 100 Series contains temperature compensation.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

Features

• 2.0 ns Worst Case Delay Range

• ≈20 ps/Delay Step Resolution

• Linear Input for Tighter Resolution

• >1.0 GHz Bandwidth

• On Chip Cascade Circuitry

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC

Latchup Test

• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3

For Additional Information, see Application Note

AND8003/D

• Flammability Rating: UL 94 V−0 @ 1.125 in,

Oxygen Index: 28 to 34

• Transistor Count = 425 devices

• Pb−Free Packages are Available*

• PECL Mode Operating Range: V = 4.2 V to 5.7 V

with V = 0 V

• NECL Mode Operating Range: V = 0 V

with V = −4.2 V to −5.7 V

• Internal Input 50 kW Pulldown Resistors

• ESD Protection: Human Body Model; > 1 kV,

Machine Model; > 75 V

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

November, 2006 − Rev. 9

MC10E196/D

12 3 4 5 6 7...12

中文翻译

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与MC100E196FNG相关器件

型号	品牌	获取价格	描述	数据表
MC100E196FNR2	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC100E196FNR2	MOTOROLA	获取价格	Active Delay Line, Programmable, 1-Func, 127-Tap, Complementary Output, ECL, PQCC28, PLAST
MC100E196FNR2G	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC100E210	ONSEMI	获取价格	5V ECL Dual 1:4, 1:5 Differential Fanout Buffer
MC100E210FN	ONSEMI	获取价格	Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer
MC100E210FN	MOTOROLA	获取价格	LOW VOLTAGE DUAL 1:4, 1:5 DIFFERENTIAL FANOUT BUFFER
MC100E210FNG	ONSEMI	获取价格	5.0 V ECL Dual 1:4, 1:5 Differential Clock/Data Fanout Buffer, 28 LEAD PLCC, 37-TUBE
MC100E210FNR2	ONSEMI	获取价格	Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer
MC100E210FNR2	MOTOROLA	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, PLASTI
MC100E210FNR2G	ONSEMI	获取价格	暂无描述

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