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MC100E212FN PDF预览

MC100E212FN

更新时间: 2024-09-30 22:46:23
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路输入元件驱动双倍数据速率
页数 文件大小 规格书
4页 115K
描述
3-BIT SCANNABLE REGISTERED ADDRESS DRIVER

MC100E212FN 技术参数

生命周期:Transferred零件包装代码:QLCC
包装说明:QCCJ, LDCC28,.5SQ针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.38Is Samacsys:N
其他特性:DIAGNOSTIC SCAN REGISTER WITH SELECTABLE SERIAL AND PARALLEL DATA INPUT; WITH PAIRED O/P'S系列:100E
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
长度:11.505 mm逻辑集成电路类型:D FLIP-FLOP
位数:3功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
电源:-4.5 V最大电源电流(ICC):110 mA
传播延迟(tpd):1.025 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Other Logic ICs
表面贴装:YES技术:ECL
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD触发器类型:POSITIVE EDGE
宽度:11.505 mmBase Number Matches:1

MC100E212FN 数据手册

 浏览型号MC100E212FN的Datasheet PDF文件第2页浏览型号MC100E212FN的Datasheet PDF文件第3页浏览型号MC100E212FN的Datasheet PDF文件第4页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10E/100E212 is a scannable registered ECL driver typically  
used as a fan-out memory address driver for ECL cache driving. In a VLSI  
array based CPU design, use of the E212 allows the user to conserve  
array output cell functionality and also output pins.  
3-BIT SCANNABLE  
REGISTERED  
The input shift register is designed with control logic which greatly  
facilitates its use in boundary scan applications.  
ADDRESS DRIVER  
Scannable Version E112 Driver  
1025ps Max. CLK to Output  
Dual Differential Outputs  
Master Reset  
Extended 100E V  
EE  
Range of – 4.2V to – 5.46V  
Internal 75kInput Pulldown Resistors  
Pinout: 28-Lead PLCC (Top View)  
FN SUFFIX  
PLASTIC PACKAGE  
CASE 776-02  
SHIFT MR  
NC S-OUTV  
Q b Q a  
CCO  
2
2
25  
24  
23  
22  
21  
20  
19  
18  
26  
27  
28  
1
Q b  
2
LOAD  
CLK  
17  
16  
15  
14  
13  
12  
Q a  
2
D
2
LOGIC DIAGRAM  
V
CC  
S-OUT  
V
Q b  
1
EE  
Q b  
2
2
D
D
Q a  
1
1
D
Q
Q a  
2
3
Q b  
1
0
D
D
D
Q a  
2
2
1
0
Q b  
2
4
Q a  
1
S-IN  
5
6
7
8
9
10  
11  
NC  
V
Q a Q b Q a Q b V  
CCO 0 0 0 0 CCO  
Q b  
1
* All V  
CC  
and V  
CCO  
pins are tied together on the die.  
D
Q
Q a  
1
Q a  
1
Q b  
1
PIN NAMES  
Pin  
Function  
D
– D  
Data Inputs  
Scan Input  
LOAD/HOLD Control  
Scan Control  
Clock  
0
2
S-IN  
Q b  
0
LOAD  
SHIFT  
CLK  
D
Q
Q a  
0
Q a  
0
Q b  
MR  
Reset  
0
S-OUT  
Q[0:2]a, Q[0:2]b  
Q[0:2]a, Q[0:2]b  
Scan Output  
True Outputs  
Inverting Outputs  
S-IN  
LOAD  
SHIFT  
CLK  
MR  
12/93  
Motorola, Inc. 1996  
REV 2  

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