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MC100E336FNR2 PDF预览

MC100E336FNR2

更新时间： 2024-01-22 19:23:40
品牌 Logo 应用领域
安森美 - ONSEMI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
8页 71K
描述
100E SERIES, 3-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQCC28, PLASTIC, LCC-28

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MC100E336FNR2 技术参数

生命周期：Transferred包装说明：QCCJ,
Reach Compliance Code：unknown风险等级：5.84
其他特性：25 OHM LINE DRIVE CAPABILITY; SYNCHRONOUS SEND ENABLE; DUAL CLOCK系列：100E
JESD-30 代码：S-PQCC-J28长度：11.5062 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER位数：3
功能数量：1端口数量：2
端子数量：28最高工作温度：85 °C
最低工作温度：输出特性：OPEN-EMITTER WITH CUT-OFF
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIER最大电源电流（ICC）：173 mA
传播延迟（tpd）：1.8 ns认证状态：Not Qualified
座面最大高度：4.57 mm表面贴装：YES
技术：ECL温度等级：OTHER
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD宽度：11.5062 mm

MC100E336FNR2 数据手册

 浏览型号MC100E336FNR2的Datasheet PDF文件第2页浏览型号MC100E336FNR2的Datasheet PDF文件第3页浏览型号MC100E336FNR2的Datasheet PDF文件第4页浏览型号MC100E336FNR2的Datasheet PDF文件第5页浏览型号MC100E336FNR2的Datasheet PDF文件第6页浏览型号MC100E336FNR2的Datasheet PDF文件第7页 
MC10E336, MC100E336  
5VĄECL 3ĆBit Registered  
Bus Transceiver  
The MC10E/MC100E336 contains three bus transceivers with both  
transmit and receive registers. The bus outputs (BUS0–BUS2) are  
specified for driving a 25 Ω bus; the receive outputs (Q0 – Q2) are  
http://onsemi.com  
MARKING  
specified for 50 Ω. The bus outputs feature a normal HIGH level (V  
)
OH  
and a cutoff LOW level — when LOW, the outputs go to –2.0 V and the  
output emitter-follower is “off”, presenting a high impedance to the bus.  
The bus outputs also feature edge slow-down capacitors.  
The Transmit Enable pins (TEN) control whether current data is  
held in the transmit register, or new data is loaded from the A/B inputs.  
A LOW on both of the Bus Enable inputs (BUSEN), when clocked  
through the register, disables the bus outputs to –2.0 V.  
The receiver section clocks bus data into the receive registers, after  
gating with the Receive Enable (RXEN) input.  
DIAGRAMS  
MC10E336FN  
AWLYYWW  
PLCC–28  
FN SUFFIX  
CASE 776  
All registers are clocked by a positive transition of CLK1 or CLK2  
(or both).  
Additional leadframe grounding is provided through the Ground  
pins (GND) which should be connected to 0 V. The GND pins are not  
electrically connected to the chip.  
28 1  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
MC100E336FN  
AWLYYWW  
The 100 Series contains temperature compensation.  
WW = Work Week  
• 25 Ω Cutoff Bus Outputs  
• 50 Ω Receiver Outputs  
28 1  
• Transmit and Receive Registers  
• 1500 ps Max. Clock to Bus  
• 1000 ps Max. Clock to Q  
• Bus Outputs Feature Internal Edge Slow-Down Capacitors  
• Additional Package Ground Pins  
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC10E336FN  
PLCC–28  
37 Units/Rail  
• PECL Mode Operating Range: V = 4.2 V to 5.7 V  
MC10E336FNR2  
MC100E336FN  
PLCC–28  
PLCC–28  
500 Units/Reel  
37 Units/Rail  
CC  
with V = 0 V  
EE  
• NECL Mode Operating Range: V = 0 V  
CC  
MC100E336FNR2  
PLCC–28  
500 Units/Reel  
with V = –4.2 V to –5.7 V  
EE  
• Internal Input Pulldown Resistors  
• ESD Protection: > 1 KV HBM, > 75 V MM  
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test  
• Moisture Sensitivity Level 1  
For Additional Information, see Application Note AND8003/D  
• Flammability Rating: UL–94 code V–0 @ 1/8”,  
Oxygen Index 28 to 34  
• Transistor Count = 430 devices  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
October, 2000 – Rev. 3  
MC10E336/D  
12345678

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