Datasheet > MC100E337

MC100E337

更新时间： 2024-09-28 22:46:23

品牌	Logo	应用领域
安森美 - ONSEMI		总线收发器
页数	文件大小	规格书
5页	120K
描述
3-BIT SCANNABLE REGISTERED BUS TRANSCEIVER

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

MC100E337 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10E/100E337 is a 3-bit registered bus transceiver with scan.

The bus outputs (BUS0–BUS2) are specified for driving a 25Ω bus; the

receive outputs (Q0 – Q2) are specified for 50Ω. The bus outputs feature

a normal HIGH level (V

) and a cutoff LOW level — when LOW, the

outputs go to – 2.0V and the output emitter-follower is “off”, presenting a

high impedance to the bus. The bus outputs also feature edge slow-down

capacitors.

3-BIT SCANNABLE

REGISTERED

BUS TRANSCEIVER

• Scannable Version of E336

• 25Ω Cutoff Bus Outputs

• 50Ω Receiver Outputs

• Scannable Registers

• Sync. and Async. Bus Enables

• Non-inverting Data Path

• 1500ps Max. Clock to Bus (Data Transmit)

• 1000ps Max. Clock to Q (Data Receive)

• Bus Outputs Feature Internal Edge Slow-Down Capacitors

• Additional Package Ground Pins

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

• Extended 100E V

Range of – 4.2V to – 5.46V

• 75kΩ Input Pulldown Resistors

Both drive and receive sides feature the same logic, including a loopback path to hold data. The HOLD/LOAD function is

controlled by Transmit Enable (TEN) and Receive Enable (REN) on the transmit and receive sides respectively, with a HIGH

selecting LOAD. Note that the implementation of the E337 Receive Enable differs from that of the E336.

A synchronous bus enable (SBUSEN) is provided for normal, non-scan operation. The asynchronous bus disable (ABUSDIS)

disables the bus immediately for scan mode.

The SYNCEN input is provided for flexibility when re-enabling the bus after disabling with ABUSDIS, allowing either

synchronous or asynchronous re-enabling. An alternative use is asynchronous-only operation with ABUSDIS, in which case

SYNCEN is tied LOW, or left open. SYNCEN is implemented as an overriding SET control (active-LOW) to the enable flip-flop.

Scan mode is selected by a HIGH at the SCAN input. Scan input data is shifted in through S_IN and output data appears at the

Q2 output.

All registers are clocked on the positive transition of CLK. Additional lead-frame grounding is provided through the Ground pins

(GND) which should be connected to 0V. The GND pins are not electrically connected to the chip.

PIN NAMES

Function

– A

– B

Data Inputs A

Data Inputs B

S-IN

Serial (Scan) Data Input

HOLD/LOAD Controls

Scan Control

TEN, REN

SCAN

ABUSDIS

SBUSEN

SYNCEN

CLK

Asynchronous Bus Disable

Synchronous Bus Enable

Synchronous Enable Control

Clock

BUS0 – BUS2

25Ω Cutoff Bus Outputs

– Q

Receive Data Outputs (Q2 serves as SCAN_OUT in scan mode)

12/93

Motorola, Inc. 1996

REV 2

2–1

12 3 4 5

中文翻译

下载PDF

与MC100E337相关器件

型号	品牌	获取价格	描述	数据表
MC100E337FN	MOTOROLA	获取价格	3-BIT SCANNABLE REGISTERED BUS TRANSCEIVER
MC100E337FNR2	MOTOROLA	获取价格	100E SERIES, 3-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PQCC28, PLASTIC, LCC-28
MC100E337FNR2	ONSEMI	获取价格	100E SERIES, 3-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PQCC28, PLASTIC, LCC-28
MC100E404	ONSEMI	获取价格	QUAD DIFFERENTIAL AND/NAND
MC100E404FN	MOTOROLA	获取价格	QUAD DIFFERENTIAL AND/NAND
MC100E404FN	ONSEMI	获取价格	5 V ECL Quad Differential AND/NAND
MC100E404FNG	ONSEMI	获取价格	5 V ECL Quad Differential AND/NAND
MC100E404FNR2	ONSEMI	获取价格	QUAD DIFFERENTIAL AND/NAND
MC100E404FNR2G	ONSEMI	获取价格	5 V ECL Quad Differential AND/NAND
MC100E416	ONSEMI	获取价格	QUINT DIFFERENTIAL LINE RECEIVER

与MC100E337相关文章

塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

27
英特尔震撼发布：128核心256线程的至强6性能核处理器
2024-09-29

23
SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

22
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

35

产品中心

服务支持

精选活动

关于我们

帮助中心

MC100E337

MC100E337 数据手册

与MC100E337相关器件

与MC100E337相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MC100E337

MC100E337 数据手册

与MC100E337相关器件

与MC100E337相关文章

您还可以找

您在本页遇到什么问题？