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MC100E431FNR2G PDF预览

MC100E431FNR2G

更新时间： 2024-10-01 05:10:27
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
9页 134K
描述
5V ECL 3-Bit Differential Flip-Flop

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中文翻译

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MC100E431FNR2G 技术参数

是否无铅： 不含铅生命周期：Lifetime Buy
零件包装代码：QLCC包装说明：LEAD FREE, PLASTIC, LCC-28
针数：28Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.67
Is Samacsys：N其他特性：NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V
系列：100EJESD-30 代码：S-PQCC-J28
JESD-609代码：e3长度：11.505 mm
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：1000000000 Hz
湿度敏感等级：3位数：1
功能数量：3端子数量：28
最高工作温度：85 °C最低工作温度：
输出特性：OPEN-EMITTER输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC28,.5SQ封装形状：SQUARE
封装形式：CHIP CARRIER包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：-4.5 V
最大电源电流（ICC）：152 mA传播延迟（tpd）：0.85 ns
认证状态：Not Qualified座面最大高度：4.57 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.7 V
最小供电电压 (Vsup)：4.2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：ECL
温度等级：OTHER端子面层：Tin (Sn)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
触发器类型：POSITIVE EDGE宽度：11.505 mm
最小 fmax：1100 MHzBase Number Matches：1

MC100E431FNR2G 数据手册

 浏览型号MC100E431FNR2G的Datasheet PDF文件第2页浏览型号MC100E431FNR2G的Datasheet PDF文件第3页浏览型号MC100E431FNR2G的Datasheet PDF文件第4页浏览型号MC100E431FNR2G的Datasheet PDF文件第5页浏览型号MC100E431FNR2G的Datasheet PDF文件第6页浏览型号MC100E431FNR2G的Datasheet PDF文件第7页 
MC10E431, MC100E431  
5VꢀECL 3-Bit Differential  
Flip-Flop  
Description  
The MC10E/100E431 is a 3-bit flip-flop with differential clock,  
data input and data output.  
http://onsemi.com  
The asynchronous Set and Reset controls are edge-triggered rather  
than level controlled. This allows the user to rapidly set or reset the  
flip-flop and then continue clocking at the next clock edge, without the  
necessity of de-asserting the set/reset signal (as would be the case with  
a level controlled set/reset).  
PLCC−28  
FN SUFFIX  
CASE 776  
The E431 is also designed with larger internal swings, an approach  
intended to minimize the time spent crossing the threshold region and  
thus reduce the metastability susceptibility window.  
MARKING DIAGRAM*  
The differential input structures are clamped so that the inputs of  
unused registers can be left open without upsetting the bias network of  
the device. The clamping action will assert the D and the CLK sides of  
the inputs. Because of the edge triggered flip-flop nature of the device  
simultaneously opening both the clock and data inputs will result in an  
output which reaches an unidentified but valid state. Note that the  
1 28  
MCxxxE431FNG  
AWLYYWW  
input clamps only operate when both inputs fall to 2.5 V below V  
.
CC  
The V pin, an internally generated voltage supply, is available to  
this device only. For single-ended input conditions, the unused  
BB  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
differential input is connected to V as a switching reference voltage.  
BB  
V
may also rebias AC coupled inputs. When used, decouple V  
BB  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
to 0.5 mA. When not used, V should be left open.  
BB  
The 100 Series contains temperature compensation.  
*For additional marking information, refer to  
Application Note AND8002/D.  
Features  
• Edge-Triggered Asynchronous Set and Reset  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
• Differential D, CLK and Q; V Reference Available  
BB  
• 1100 MHz Min. Toggle Frequency  
• PECL Mode Operating Range: V = 4.2 V to 5.7 V  
CC  
with V = 0 V  
EE  
• NECL Mode Operating Range: V = 0 V  
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3  
For Additional Information, see Application Note  
AND8003/D  
• Flammability Rating: UL 94 V−0 @ 0.125 in,  
Oxygen Index: 28 to 34  
CC  
with V = −4.2 V to −5.7 V  
EE  
• Internal Input 50 kW Pulldown Resistors  
• ESD Protection: Human Body Model; > 2 kV,  
Machine Model; > 200 V  
• Transistor Count = 348 devices  
• Pb−Free Packages are Available*  
Charged Device Model; > 2 kV  
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC  
Latchup Test  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 10  
MC10E431/D  
1234567...9

中文翻译

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MC100E431FNR2G 替代型号

型号 品牌 替代类型 描述 数据表
MC100E131FNG ONSEMI

类似代替

 5V ECL 4-Bit D Flip-Flop
MC100E431FN ONSEMI

类似代替

 5V ECL 3-Bit Differential Flip-Flop

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