MC100E452

更新时间： 2024-11-19 22:46:23

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
4页	115K
描述
5-BIT DIFFERENTIAL REGISTER

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数据手册

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MC100E452 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10E/100E452 is a 5-bit differential register with differential data

(inputs and outputs) and clock. The registers are triggered by a positive

transition of the positive clock (CLK) input. A high on the Master Reset

(MR) asynchronously resets all registers so that the Q outputs go LOW.

The differential input structures are clamped so that the inputs of

unused registers can be left open without upsetting the bias network of

the device. The clamping action will assert the D and the CLK sides of the

inputs. Because of the edge triggered flip-flop nature of the device

simultaneously opening both the clock and data inputs will result in an

output which reaches an unidentified but valid state. Note that the input

5-BIT DIFFERENTIAL

clamps only operate when both inputs fall to 2.5V below V

The fully differential design of the device makes it ideal for very high

frequency applications where a registered data path is necessary.

• Differential D, CLK and Q; V

Reference Available

• 1100MHz Min. Toggle Frequency

• Asynchronous Master Reset

• Extended 100E V

Range of – 4.2V to – 5.46V

Pinout: 28-Lead PLCC (Top View)

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

CCO

CLK

LOGIC DIAGRAM

CCO

* All V

and V

CCO

pins are tied together on the die.

PIN NAMES

Function

D[0:4], D[0:4]

CLK, CLK

VBB

Differential Data Inputs

Master Reset Input

Differential Clock Input

VBB Reference Output

Differential Data Outputs

CLK

Q[0:4], Q[0:4]

12/93

Motorola, Inc. 1996

REV 2

2–1

12 3 4

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MC100E457FN	ONSEMI	获取价格	5V ECL Triple Differential 2:1 Multiplexer
MC100E457FN	ROCHESTER	获取价格	100E SERIES, TRIPLE 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PQCC28, PLASTIC, L
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