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MC100E457FN PDF预览

MC100E457FN

更新时间: 2024-11-19 22:46:23
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 解复用器逻辑集成电路
页数 文件大小 规格书
5页 114K
描述
TRIPLE DIFFERENTIAL 2:1 MULTIPLEXER

MC100E457FN 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:QCCJ, LDCC28,.5SQReach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.7
系列:100EJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.5062 mm
逻辑集成电路类型:MULTIPLEXER功能数量:3
输入次数:2输出次数:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C输出特性:OPEN-EMITTER
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
电源:-4.5 V最大电源电流(ICC):127 mA
Prop。Delay @ Nom-Sup:0.7 ns传播延迟(tpd):0.775 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Multiplexer/Demultiplexers表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:11.5062 mmBase Number Matches:1

MC100E457FN 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10E457/100E457 is a 3-bit differential 2:1 multiplexer. The fully  
differential data path makes the device ideal for multiplexing low skew  
clock or other skew sensitive signals. Multiple V  
ease AC coupling input signals.  
pins are provided to  
BB  
The higher frequency outputs provide the device with a >1.0GHz  
bandwidth to meet the needs of the most demanding system clock.  
TRIPLE DIFFERENTIAL  
2:1 MULTIPLEXER  
Both, separate selects and a common select, are provided to make the  
device well suited for both data path and random logic applications.  
The differential inputs have internal clamp structures which will force  
the Q output of a gate in an open input condition to go to a LOW state.  
Thus, inputs of unused gates can be left open and will not affect the  
operation of the rest of the device. Note that the input clamp will take  
affect only if both inputs fall 2.5V below V  
.
CC  
Differential D and Q; V  
BB  
available  
700ps Max. Propagation Delay  
High Frequency Outputs  
FN SUFFIX  
PLASTIC PACKAGE  
CASE 776-02  
Separate and Common Select  
Extended 100E V  
EE  
Range of –4.2V to –5.46V  
Internal 75kInput Pulldown Resistors  
Pinout: 28-Lead PLCC (Top View)  
SEL2 D a  
D a  
2
V
D b  
2
D b COMSEL  
2
2
BB  
25  
24  
23  
22  
21  
20  
19  
PIN NAMES  
18  
Q
Q
SEL1  
26  
2
Pin  
Function  
Dn[0:2]; Dn[0:2]  
SEL  
COMSEL  
Differential Data Inputs  
Individual Select Input  
Common Select Input  
17  
16  
D a  
1
27  
28  
2
D a  
V
CC  
1
V
BB  
V
BB  
Reference Output  
Q[0:2], Q[0:2]  
Differential Data Outputs  
1
15  
14  
13  
V
Q
Q
Q
Q
EE  
BB  
1
1
0
0
2
3
4
V
FUNCTION TABLE  
SEL  
D b  
1
Data  
D b  
1
12  
H
L
a
b
5
6
7
D a  
8
9
D b  
10  
D b  
11  
SEL0 D a  
V
V
CCO  
0
0
BB  
0
0
* All V  
and V  
pins are tied together on the die.  
CC  
CCO  
12/93  
REV 2  
Motorola, Inc. 1996  

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