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MC100E457FNR2 PDF预览

MC100E457FNR2

更新时间： 2024-10-01 05:10:27
品牌 Logo 应用领域
安森美 - ONSEMI 复用器逻辑集成电路
页数 文件大小 规格书
9页 136K
描述
5V ECL Triple Differential 2:1 Multiplexer

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MC100E457FNR2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QLCC包装说明：PLASTIC, LCC-28
针数：28Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：7.52
其他特性：NECL MODE OPERATING RANGE: VEE = -4.2 V TO -5.7 V WITH VCC = 0 V系列：100E
JESD-30 代码：S-PQCC-J28JESD-609代码：e0
长度：11.505 mm逻辑集成电路类型：MULTIPLEXER
湿度敏感等级：1功能数量：3
输入次数：2输出次数：1
端子数量：28最高工作温度：85 °C
最低工作温度：输出特性：OPEN-EMITTER
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：240
电源：-4.5 V最大电源电流（ICC）：127 mA
Prop。Delay @ Nom-Sup：0.7 ns传播延迟（tpd）：0.7 ns
认证状态：Not Qualified座面最大高度：4.57 mm
子类别：Multiplexer/Demultiplexers最大供电电压 (Vsup)：5.7 V
最小供电电压 (Vsup)：4.2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：ECL
温度等级：OTHER端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：11.505 mmBase Number Matches：1

MC100E457FNR2 数据手册

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MC10E457, MC100E457  
5VꢀECL Triple Differential  
2:1 Multiplexer  
Description  
The MC10E457/100E457 is a 3-bit differential 2:1 multiplexer. The  
fully differential data path makes the device ideal for multiplexing low  
skew clock or other skew sensitive signals.  
http://onsemi.com  
The higher frequency outputs provide the device with a > 1.0 GHz  
bandwidth to meet the needs of the most demanding system clock.  
Both, separate selects and a common select, are provided to make  
the device well suited for both data path and random logic  
applications.  
PLCC−28  
FN SUFFIX  
CASE 776  
The differential inputs have internal clamp structures which will  
force the Q output of a gate in an open input condition to go to a LOW  
state. Thus, inputs of unused gates can be left open and will not affect  
the operation of the rest of the device. Note that the input clamp will  
MARKING DIAGRAM*  
1 28  
take affect only if both inputs fall 2.5 V below V  
.
CC  
The 100 Series contains temperature compensation.  
Multiple V pins are provided to ease AC coupling input signals.  
MCxxxE457FNG  
AWLYYWW  
BB  
The V pins, internally generated voltage supply pins, are available  
BB  
to this device only. For single-ended input conditions, the unused  
differential input is connected to V as a switching reference voltage.  
BB  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
to 0.5 mA. When not used, V should be left open.  
BB  
Features  
• Differential D and Q; V available  
BB  
*For additional marking information, refer to  
Application Note AND8002/D.  
• 700 ps Max. Propagation Delay  
• High Frequency Outputs  
• Separate and Common Select  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
• PECL Mode Operating Range: V = 4.2 V to 5.7 V  
CC  
with V = 0 V  
EE  
• NECL Mode Operating Range: V = 0 V  
CC  
with V = −4.2 V to −5.7 V  
EE  
• Internal Input 50 kW Pulldown Resistors  
• ESD Protection: Human Body Model; > 2 kV,  
Machine Model; > 200 V  
• Flammability Rating: UL 94 V−0 @ 0.125 in,  
Oxygen Index: 28 to 34  
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC  
Latchup Test  
• Transistor Count = 218 devices  
• Pb−Free Packages are Available*  
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3  
For Additional Information, see Application Note  
AND8003/D  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 8  
MC10E457/D  
1234567...9

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