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MC100E451FN

更新时间： 2024-10-01 05:10:27
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路时钟
页数 文件大小 规格书
9页 134K
描述
5V ECL 6−Bit D Register Differential Data and Clock

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MC100E451FN 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QLCC包装说明：PLASTIC, LCC-28
针数：28Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.54
Is Samacsys：N其他特性：NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V
系列：100EJESD-30 代码：S-PQCC-J28
JESD-609代码：e0长度：11.505 mm
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：1100000000 Hz
湿度敏感等级：1位数：6
功能数量：1端子数量：28
最高工作温度：85 °C最低工作温度：
输出特性：OPEN-EMITTER输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC28,.5SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：240
电源：-4.5 V最大电源电流（ICC）：116 mA
传播延迟（tpd）：1.05 ns认证状态：Not Qualified
座面最大高度：4.57 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.7 V最小供电电压 (Vsup)：4.2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：ECL温度等级：OTHER
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30触发器类型：POSITIVE EDGE
宽度：11.505 mm最小 fmax：1100 MHz
Base Number Matches：1

MC100E451FN 数据手册

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MC10E451, MC100E451  
5VꢀECL 6−Bit D Register  
Differential Data and Clock  
Description  
The MC10E/100E451 contains six D−type flip−flops with  
single−ended outputs and differential data inputs. The common clock  
input is also differential. The registers are triggered by a positive  
transition of the positive clock (CLK) input.  
A HIGH on the Master Reset (MR) input resets all Q outputs to  
LOW.  
The differential input structures are clamped so that the inputs of  
unused registers can be left open without upsetting the bias network of  
the device. The clamping action will assert the D and the CLK sides of  
the inputs. Because of the edge triggered flip−flop nature of the device  
simultaneously opening both the clock and data inputs will result in an  
output which reaches an unidentified but valid state. Note that the  
http://onsemi.com  
PLCC−28  
FN SUFFIX  
CASE 776  
MARKING DIAGRAM*  
1 28  
input clamps only operate when both inputs fall to 2.5 V below V  
.
CC  
The V pin, an internally generated voltage supply, is available to  
this device only. For single−ended input conditions, the unused  
BB  
MCxxxE451FNG  
AWLYYWW  
differential input is connected to V as a switching reference voltage.  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
to 0.5 mA. When not used, V should be left open.  
BB  
The 100 Series contains temperature compensation.  
Features  
• Differential Inputs: Data and Clock  
• V Output  
• 1100 MHz Min. Toggle Frequency  
• Asynchronous Master Reset  
BB  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
• PECL Mode Operating Range:  
V
= 4.2 V to 5.7 V with V = 0 V  
CC  
EE  
• NECL Mode Operating Range:  
= 0 V with V = −4.2 V to −5.7 V  
V
CC  
EE  
• Internal Input 50 kW Pulldown Resistors  
• ESD Protection: Human Body Model; > 2 kV,  
Machine Model; > 200 V  
• Transistor Count = 348 devices  
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC  
Latchup Test  
• Moisture Sensitivity Level:  
Pb = 1;  
Pb−Free = 3  
For Additional Information, see Application Note  
AND8003/D  
• Pb−Free Packages are Available*  
• Flammability Rating: UL 94 V−0 @ 0.125 in,  
Oxygen Index: 28 to 34  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 9  
MC10E451/D  
1234567...9

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MC100E451FN 替代型号

型号 品牌 替代类型 描述 数据表
MC100E451FNG ONSEMI

完全替代

 5V ECL 6−Bit D Register Differential Data and Clock

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