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MC100E310 PDF预览

MC100E310

更新时间: 2024-01-16 11:31:49
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 134K
描述
5V ECL Low Voltage 2:8 Differential Fanout Buffer

MC100E310 技术参数

是否无铅: 含铅生命周期:Active
零件包装代码:QLCC包装说明:LEAD FREE, PLASTIC, LCC-28
针数:28Reach Compliance Code:unknown
风险等级:5.72其他特性:NECL MODE: 0V VCC WITH VEE = -4.2V TO -5.7V
系列:100E输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.505 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:NOT SPECIFIED功能数量:1
反相输出次数:端子数量:28
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):260
传播延迟(tpd):0.8 ns认证状态:COMMERCIAL
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:4.57 mm
最大供电电压 (Vsup):5.7 V最小供电电压 (Vsup):4.2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:11.505 mm
最小 fmax:700 MHzBase Number Matches:1

MC100E310 数据手册

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MC100E310  
5VꢀECL Low Voltage 2:8  
Differential Fanout Buffer  
Description  
The MC100E310 is a low voltage, low skew 2:8 differential ECL  
fanout buffer designed with clock distribution in mind. The device  
features fully differential clock paths to minimize both device and  
system skew. The E310 offers two selectable clock inputs to allow for  
redundant or test clocks to be incorporated into the system clock trees.  
The lowest TPD delay time results from terminating only one output  
pair, and the greatest TPD delay time results from terminating all the  
output pairs. This shift is about 1020 pS in TPD. The skew between  
any two output pairs within a device is typically about 25 nS. If other  
output pairs are not terminated, the lowest TPD delay time results  
from both output pairs and the skew is typically 25 nS. When all  
outputs are terminated, the greatest TPD (delay time) occurs and all  
outputs display about the same 10 20 ps increase in TPD, so the  
relative skew between any two output pairs remains about 25 ns.  
For more information on using PECL, designers should refer to  
ON Semiconductor Application Note AN1406/D.  
http://onsemi.com  
PLCC28  
FN SUFFIX  
CASE 776  
MARKING DIAGRAM*  
1 28  
MC100E310FNG  
AWLYYWW  
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single-ended input conditions, the unused  
A
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
differential input is connected to V as a switching reference voltage.  
BB  
WL  
YY  
WW  
G
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
to 0.5 mA. When not used, V should be left open.  
BB  
The 100 Series Contains Temperature Compensation  
*For additional marking information, refer to  
Application Note AND8002/D.  
Features  
Dual Differential Fanout Buffers  
200 ps ParttoPart Skew  
50 ps OutputtoOutput Skew  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
28lead PLCC Packaging  
Q Output will Default LOW with Inputs Open or at V  
EE  
PECL Mode Operating Range: V = 4.2 V to 5.7 V  
Moisture Sensitivity Level: Pb = 1; PbFree = 3  
For Additional Information, see Application Note  
AND8003/D  
Flammability Rating: UL 94 V0 @ 0.125 in,  
Oxygen Index: 28 to 34  
Transistor Count = 212 devices  
PbFree Packages are Available*  
CC  
with V = 0 V  
EE  
NECL Mode Operating Range: V = 0 V  
CC  
with V = 4.2 V to 5.7 V  
EE  
Internal Input 50 kW Pulldown Resistors  
ESD Protection: Human Body Model; >2 kV,  
Machine Model; >200 V  
Meets or Exceeds JEDEC Spec EIA/JESD78 IC  
Latchup Test  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
October, 2006 Rev. 5  
MC100E310/D  

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