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MC100E310FN PDF预览

MC100E310FN

更新时间: 2024-09-28 22:46:23
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟驱动器逻辑集成电路
页数 文件大小 规格书
6页 111K
描述
LOW VOLTAGE 2:8 DIFFERENTIAL FANOUT BUFFER

MC100E310FN 技术参数

生命周期:Transferred零件包装代码:QLCC
包装说明:QCCJ, LDCC28,.5SQ针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.42Is Samacsys:N
系列:100E输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
长度:11.5062 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:28实输出次数:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:-4.5 V
Prop。Delay @ Nom-Sup:0.85 ns传播延迟(tpd):0.85 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.05 ns
座面最大高度:4.57 mm子类别:Clock Drivers
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:11.5062 mmBase Number Matches:1

MC100E310FN 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC100LVE310 is a low voltage, low skew 2:8 differential ECL  
fanout buffer designed with clock distribution in mind. The device features  
fully differential clock paths to minimize both device and system skew.  
The LVE310 offers two selectable clock inputs to allow for redundant or  
test clocks to be incorporated into the system clock trees. The  
MC100E310 is pin compatible to the National 100310 device. The  
MC100LVE310 works from a –3.3V supply while the MC100E310  
provides identical function and performance from a standard –4.5V 100E  
voltage supply.  
LOW VOLTAGE  
2:8 DIFFERENTIAL  
FANOUT BUFFER  
Dual Differential Fanout Buffers  
200ps Part–to–Part Skew  
50ps Output–to–Output Skew  
Low Voltage ECL/PECL Compatible  
28–lead PLCC Packaging  
For applications which require a single–ended input, the V  
reference  
BB  
voltage is supplied. For single–ended input applications the V  
BB  
reference should be connected to the CLK input and bypassed to ground  
FN SUFFIX  
PLASTIC PACKAGE  
CASE 776–02  
via a 0.01µf capacitor. The input signal is then driven into the CLK input.  
To ensure that the tight skew specification is met it is necessary that  
both sides of the differential output are terminated into 50, even if only  
one side is being used. In most applications all nine differential pairs will  
be used and therefore terminated. In the case where fewer than nine  
pairs are used it is necessary to terminate at least the output pairs  
adjacent to the output pair being used in order to maintain minimum skew.  
Failure to follow this guideline will result in small degradations of  
propagation delay (on the order of 10–20ps) of the outputs being used,  
while not catastrophic to most designs this will result in an increase in  
skew. Note that the package corners isolate outputs from one another  
such that the guideline expressed above holds only for outputs on the  
same side of the package.  
The MC100LVE310, as with most ECL devices, can be operated from a positive V  
supply in PECL mode. This allows the  
CC  
LVE310 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE310’s  
performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line  
terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage  
of V –2.0V will need to be provided. For more information on using PECL, designers should refer to Motorola Application Note  
CC  
AN1406/D.  
7/95  
REV 0.1  
Motorola, Inc. 1996  

MC100E310FN 替代型号

型号 品牌 替代类型 描述 数据表
SY100E310LJYTR MICREL

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MC100LVE310FN MOTOROLA

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LOW VOLTAGE 2:8 DIFFERENTIAL FANOUT BUFFER

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