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SY100E310LJYTR PDF预览

SY100E310LJYTR

更新时间: 2024-11-24 07:17:11
品牌 Logo 应用领域
麦瑞 - MICREL 时钟驱动器逻辑集成电路
页数 文件大小 规格书
6页 71K
描述
3.3V ECL/PECL 2:8 DIFFERENTIAL FANOUT BUFFER

SY100E310LJYTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:QLCC
包装说明:QCCJ,针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.16Is Samacsys:N
系列:100E输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.48 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:2功能数量:1
反相输出次数:端子数量:28
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):245
传播延迟(tpd):0.75 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:4.57 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:11.48 mm
Base Number Matches:1

SY100E310LJYTR 数据手册

 浏览型号SY100E310LJYTR的Datasheet PDF文件第2页浏览型号SY100E310LJYTR的Datasheet PDF文件第3页浏览型号SY100E310LJYTR的Datasheet PDF文件第4页浏览型号SY100E310LJYTR的Datasheet PDF文件第5页浏览型号SY100E310LJYTR的Datasheet PDF文件第6页 
3.3V ECL/PECL  
2:8 DIFFERENTIAL FANOUT BUFFER  
SY100E310L  
DESCRIPTION  
FEATURES  
Guaranteed AC performance over temperature and  
The SY100E310L is a 3.3V, precision 2:8 ECL/PECL  
fanout buffer optimized for precision low-skew clock  
distribution. The SY100E310L features fully differential clock  
paths to minimize both device and system skew resulting in  
skew performance of < 50ps. In addition, the device includes  
a 2:1 multiplexer input for redundant switchover applications.  
voltage:  
• > 800MHz f  
(typical)  
MAX  
• < 50ps within-device skew  
Low voltage operation:  
• LVPECL: +3.3V ±10%  
The SY100E310L is optimized for low voltage +3.3V  
LVPECL or –3.3V LVECL applications.  
• LVECL: –3.3V ±10%  
Internal 75kpull-down resistors  
Guaranteed over industrial temperature range:  
–40°C to +85°C  
Data sheets and support documentation can be found on  
Micrel’s web site at www.micrel.com.  
Pin-for-pin, plug-in replacement for MC100LVE310  
Available in 28-pin PLCC package  
APPLICATIONS  
CROSS REFERENCE TABLE  
Communications clock distribution  
Redundant clock switchover  
Micrel Semiconductor  
SY100E310LJI  
On Semiconductor  
MC100LVE310FN  
MC100LVE310FNR2  
High-end server clock distribution  
SY100E310LJITR  
FUNCTIONAL BLOCK DIAGRAM  
TYPICAL PERFORMANCE  
Q0  
Output Swing  
vs. Frequency  
/Q0  
Q1  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
/Q1  
Q2  
/Q2  
CLKA  
Q3  
/CLKA  
/Q3  
Q4  
CLKB  
/CLKB  
/Q4  
Q5  
SEL  
CLK FREQUENCY (MHz)  
/Q5  
Q6  
/Q6  
Q7  
VBB  
/Q7  
Rev.: D  
Amendment: /1  
M9999-072106  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: July 2006  

SY100E310LJYTR 替代型号

型号 品牌 替代类型 描述 数据表
SY100E310LJI MICREL

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