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SY100E416JCTR

更新时间： 2024-11-19 22:42:35

品牌	Logo	应用领域
麦瑞 - MICREL		接口集成电路
页数	文件大小	规格书
4页	63K
描述
QUINT DIFFERENTIAL LINE RECEIVER

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中文翻译

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数据手册

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SY100E416JCTR 数据手册

9-BIT

BUFFER

SY10E122

SY100E122

FEATURES

DESCRIPTION

■ 500ps max. propagation delay

The SY10/100E122 are 9-bit buffers designed for use in

new, high-performance ECL systems. The E122 provides

nine non-inverting buffers.

■ Extended 100E VEE range of –4.2V to –5.5V

■ Fully compatible with industry standard 10KH,

100K I/O levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E122

■ Available in 28-pin PLCC package

BLOCK DIAGRAM

PIN CONFIGURATION

24 23 22 21 20 19

VCC

PLCC

TOP VIEW

J28-1

VEE

VCCO

10 11

PIN NAMES

D0-D8

Q0-Q8

VCCO

Function

Data Inputs

Data Outputs

VCC to Output

Rev.: D

Amendment: /2

Issue Date: May, 1998

12 3 4

中文翻译

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