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SY100E337JCTR PDF预览

SY100E337JCTR

更新时间： 2024-11-19 22:13:39
品牌 Logo 应用领域
麦瑞 - MICREL /
页数 文件大小 规格书
4页 68K
描述
3-BIT SCANNABLE

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中文翻译

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SY100E337JCTR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：PLASTIC, LCC-28Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.5
其他特性：25 OHM LINE DRIVE CAPABILITY; ADDITIONAL SYNCHRONOUS SEND ENABLE; SERIAL SHIFT IN DATA FOR SCAN控制类型：INDEPENDENT CONTROL
计数方向：UNIDIRECTIONAL系列：100E
JESD-30 代码：S-PQCC-J28JESD-609代码：e0
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER位数：3
功能数量：1端口数量：2
端子数量：28最高工作温度：85 °C
最低工作温度：输出特性：OPEN-EMITTER WITH CUT-OFF
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
包装方法：TAPE AND REEL电源：-4.5 V
最大电源电流（ICC）：200 mAProp。Delay @ Nom-Sup：1 ns
传播延迟（tpd）：1 ns认证状态：Not Qualified
子类别：Bus Driver/Transceivers表面贴装：YES
技术：ECL温度等级：OTHER
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
翻译：N/A触发器类型：POSITIVE EDGE

SY100E337JCTR 数据手册

 浏览型号SY100E337JCTR的Datasheet PDF文件第2页浏览型号SY100E337JCTR的Datasheet PDF文件第3页浏览型号SY100E337JCTR的Datasheet PDF文件第4页 
3-BIT SCANNABLE  
REGISTERED BUS  
TRANSCEIVER  
SY10E337  
SY100E337  
FEATURES  
DESCRIPTION  
■ 1500ps max. clock to bus (data transmit)  
■ 1000ps max. clock to Q (data receive)  
■ Extended 100E VEE range of –4.2V to –5.5V  
■ 25Ω cutoff bus outputs  
The SY10/100E337 are 3-bit registered bus transceivers  
with scan designed for use in new, high- performance ECL  
systems. The bus outputs (BUS0–BUS2) are designed to  
drive a 25Ω bus; the receive outputs (Q0–Q2) are designed  
for 50Ω. The bus outputs feature a normal logic HIGH level  
(VOH) and a cutoff LOW level of –2.0V and the output  
emitter-follower is “off”, presenting a high impedance to the  
bus. The bus outputs also feature edge slow-down  
capacitors.  
Both drive and receive sides feature the same logic,  
including a loopback path to hold data. The LOAD/HOLD  
functioniscontrolledbyTransmitEnable(TEN)andReceive  
Enable (REN) on the transmit and receive sides,  
respectively, with a HIGH selecting LOAD. The  
implementation of the E337 Receive Enable differs from  
that of the E336.  
■ 50Ω receiver outputs  
■ Scannable implementation of E336  
■ Synchronous and asynchronous bus enables  
■ Non-inverting data path  
■ Bus outputs feature internal edge slow-down  
capacitors  
■ Additional package ground pins  
■ Fully compatible with industry standard 10KH,  
100K ECL levels  
■ Internal 75KΩ input pulldown resistors  
■ Fully compatible with Motorola MC10E/100E337  
■ Available in 28-pin PLCC package  
A synchronous bus enable (SBUSEN) is provided for  
normal, non-scan operation. The asynchronous bus disable  
(ABUSDIS) disables the bus for scan mode.  
The SYNCEN input allows either synchronous or  
asynchronous re-enabling after disabling with ABUSDIS.  
An alternative use is asynchronous-only operation with  
ABUSDIS, in which case SYNCEN is tied LOW. SYNCEN  
is implemented as an overriding SET control to the enable  
flip-flop.  
PIN CONFIGURATION  
Scan mode is selected by a logic HIGH at the SCAN  
input. Scan input data is shifted in through S-IN, and output  
data appears at the Q2 output.  
All registers are clocked on the rising edge of CLK.  
Additional lead-frame grounding is provided through the  
ground pins (GND) which should be connected to 0V. The  
GND pins are not electrically connected to the chip.  
25 24 23 22 21 20 19  
SCAN  
S-IN  
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
GND  
BUS  
0
PIN NAMES  
TEN  
VCC  
TOP VIEW  
PLCC  
VEE  
Q
1
Pin  
Function  
Data Inputs A  
J28-1  
REN  
CLK  
2
VCCO  
A0–A2  
3
BUS  
1
B0–B2  
Data Inputs B  
A1  
4
GND  
S-IN  
Serial (Scan) Data Input  
LOAD/HOLD Controls  
Scan Control  
5
6
7
8
9
10 11  
TEN, REN  
SCAN  
ABUSDIS  
SBUSEN  
SYNCEN  
CLK  
Asynchronous Bus Disable  
Synchronous Bus Enable  
Synchronous Enable Control  
Clock  
BUS0–BUS2  
Q0–Q2  
25Ω Cutoff BUS Outputs  
Receive Data Outputs (Q2 serves as  
SCAN_OUT in scan mode)  
VCCO  
VCC to Output  
Rev.: C  
Amendment: /2  
Issue Date: February, 1998  
1
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