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SY100E404JC

更新时间： 2024-01-19 19:48:19

品牌	Logo	应用领域
麦瑞 - MICREL		栅极触发器逻辑集成电路
页数	文件大小	规格书
4页	63K
描述
QUAD DIFFERENTIAL AND/NAND

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技术参数
数据手册

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SY100E404JC 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	QCCJ,	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.76
系列：	100E	JESD-30 代码：	S-PQCC-J28
JESD-609代码：	e3	长度：	11.48 mm
逻辑集成电路类型：	AND/NAND GATE	湿度敏感等级：	2
功能数量：	4	输入次数：	2
端子数量：	28	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	260
传播延迟（tpd）：	0.725 ns	认证状态：	Not Qualified
座面最大高度：	4.57 mm	表面贴装：	YES
技术：	ECL	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	11.48 mm
Base Number Matches：	1

SY100E404JC 数据手册

QUAD DIFFERENTIAL

AND/NAND

SY10E404

SY100E404

DESCRIPTION

FEATURES

■ Differential D and Q

The SY10/100E404 are 4-bit differential AND/NAND

devices. The differential operation of these devices make

them ideal for pulse shaping applications where duty cycle

skew is critical. Special design techniques were

incorporated to minimize the skew between the upper

and lower level gate inputs.

Because a negative 2-input NAND function is

equivalent to a 2-input OR function, the differential inputs

and outputs of the devices also allow for their use as

fully differential 2-input OR/NOR functions.

■ Extended 100E VEE range of –4.2V to –5.5V

■ 700ps max. propagation delay

■ High frequency outputs

■ Internal 75KΩ input pull-down resistors

■ Fully compatible with Motorola 10E/100E404

■ Available in 28-pin PLCC package

The output RISE/FALL times of these devices are

significantly faster than most other standard ECLinPS

devices, resulting in an increased bandwidth.

The differential inputs have clamp structures which

will force the Q output of a gate in an open input condition

to go to a LOW state. Thus, inputs of unused gates can

be left open and will not affect the operation of the rest

of the device.

PIN CONFIGURATION

BLOCK DIAGRAM

D0a

D0b

24 23 22 21 20 19

D2b

D2a

VEE

D2a

D1b

VCC

TOP VIEW

PLCC

J28-1

D2a

D2b

10 11

D3a

D3b

PIN NAMES

Function

D[0:4], D[0:4]

Q[0:4], Q[0:4]

VCCO

Differential Data Inputs

Differential Data Outputs

VCC to Output

Rev.: D

Amendment:/1

Issue Date: February, 1998

12 3 4

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