Datasheet > 逻辑 > 总线驱动器/收发器> SY100E337JZTR

SY100E337JZTR

更新时间： 2024-09-29 03:09:07

品牌	Logo	应用领域
麦瑞 - MICREL		总线收发器逻辑集成电路
页数	文件大小	规格书
5页	67K
描述
3-BIT SCANNABLE REGISTERED BUS TRANSCEIVER

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SY100E337JZTR 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
零件包装代码：	QLCC	包装说明：	QCCJ,
针数：	28	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.43
系列：	100E	JESD-30 代码：	S-PQCC-J28
JESD-609代码：	e3	长度：	11.48 mm
逻辑集成电路类型：	REGISTERED BUS TRANSCEIVER	位数：	3
功能数量：	1	端口数量：	2
端子数量：	28	最高工作温度：	85 °C
最低工作温度：		输出特性：	OPEN-EMITTER WITH CUT-OFF
输出极性：	TRUE	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	传播延迟（tpd）：	1 ns
认证状态：	Not Qualified	座面最大高度：	4.57 mm
表面贴装：	YES	技术：	ECL
温度等级：	COMMERCIAL EXTENDED	端子面层：	MATTE TIN
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	11.48 mm
Base Number Matches：	1

SY100E337JZTR 数据手册

SY10E337

3-BIT SCANNABLE

REGISTERED BUS

TRANSCEIVER

SY100E337

Micrel, Inc.

SY10E337

SY100E337

FEATURES

DESCRIPTION

■ 1500ps max. clock to bus (data transmit)

■ 1000ps max. clock to Q (data receive)

■ Extended 100E VEE range of –4.2V to –5.5V

■ 25Ω cutoff bus outputs

The SY10/100E337 are 3-bit registered bus transceivers

with scan designed for use in new, high- performance ECL

systems. The bus outputs (BUS0–BUS2) are designed to

drive a 25Ω bus; the receive outputs (Q0–Q2) are designed

for 50Ω. The bus outputs feature a normal logic HIGH level

(VOH) and a cutoff LOW level of –2.0V and the output

emitter-follower is “off”, presenting a high impedance to the

bus. The bus outputs also feature edge slow-down

capacitors.

Both drive and receive sides feature the same logic,

including a loopback path to hold data. The LOAD/HOLD

functioniscontrolledbyTransmitEnable(TEN)andReceive

Enable (REN) on the transmit and receive sides,

respectively, with a HIGH selecting LOAD. The

implementation of the E337 Receive Enable differs from

that of the E336.

■ 50Ω receiver outputs

■ Scannable implementation of E336

■ Synchronous and asynchronous bus enables

■ Non-inverting data path

■ Bus outputs feature internal edge slow-down

capacitors

■ Additional package ground pins

■ Fully compatible with industry standard 10KH,

100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E337

■ Available in 28-pin PLCC package

A synchronous bus enable (SBUSEN) is provided for

normal, non-scan operation. The asynchronous bus disable

(ABUSDIS) disables the bus for scan mode.

The SYNCEN input allows either synchronous or

asynchronous re-enabling after disabling with ABUSDIS.

An alternative use is asynchronous-only operation with

ABUSDIS, in which case SYNCEN is tied LOW. SYNCEN

is implemented as an overriding SET control to the enable

flip-flop.

Scan mode is selected by a logic HIGH at the SCAN

input. Scan input data is shifted in through S-IN, and output

data appears at the Q2 output.

All registers are clocked on the rising edge of CLK.

Additional lead-frame grounding is provided through the

ground pins (GND) which should be connected to 0V. The

GND pins are not electrically connected to the chip.

PIN NAMES

Function

Data Inputs A

A0–A2

B0–B2

Data Inputs B

S-IN

Serial (Scan) Data Input

LOAD/HOLD Controls

Scan Control

TEN, REN

SCAN

ABUSDIS

SBUSEN

SYNCEN

CLK

Asynchronous Bus Disable

Synchronous Bus Enable

Synchronous Enable Control

Clock

BUS0–BUS2

Q0–Q2

25Ω Cutoff BUS Outputs

Receive Data Outputs (Q2 serves as

SCAN_OUT in scan mode)

VCCO

VCC to Output

Rev.: F

Amendment: /0

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4 5

中文翻译

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