MC100E256

更新时间： 2024-09-29 12:46:39

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
5页	113K
描述
3-BIT 4:1 MUX-LATCH

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中文翻译

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数据手册

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MC100E256 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10E/100E256 contains three 4:1 multiplexers followed by

transparent latches with differential outputs. Separate Select controls are

provided for the leading 2:1 mux pairs (see logic symbol).

When the Latch Enable (LEN) is LOW, the latch is transparent, and

output data is controlled by the multiplexer select controls. A logic HIGH

on LEN latches the outputs. The Master Reset (MR) overrides all other

controls to set the Q outputs LOW.

3-BIT 4:1

MUX-LATCH

• 950ps Max. D to Output

• 850ps Max. LEN to Output

• Split Select

• Differential Outputs

• Extended 100E V

Range of – 4.2V to – 5.46V

• 75kΩ Input Pulldown Resistors

Pinout: 28-Lead PLCC (Top View)

CCO

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

SEL1A

SEL1B

SEL2

LEN

CCO

* All V

and V

pins are tied together on the die.

CCO

FUNCTION TABLE

PIN NAMES

Function

State

Operation

– D

Data Inputs

SEL2

SEL1A

SEL1B

Output c/d Data

Input d Data

Input b Data

SEL1A, SEL1B

First-stage Select Inputs

Second-stage Select input

Latch Enable

SEL2

LEN

Master Reset

Q , Q – Q , Q

Data Outputs

12/93

Motorola, Inc. 1996

REV 2

2–1

12 3 4 5

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