MC100E210

更新时间： 2024-10-01 05:10:27

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
8页	65K
描述
5V ECL Dual 1:4, 1:5 Differential Fanout Buffer

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MC100E210 数据手册

MC100E210

5VꢀECL Dual 1:4, 1:5

Differential Fanout Buffer

The MC100E210 is a low voltage, low skew dual differential ECL

fanout buffer designed with clock distribution in mind. The device

features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The

device features fully differential clock paths to minimize both device and

system skew. The dual buffer allows for the fanout of two signals through

a single chip, thus reducing the skew between the two fundamental

signals from a part−to−part skew down to an output−to−output skew. This

capability reduces the skew by a factor of 4 as compared to using two

LVE111’s to accomplish the same task.

http://onsemi.com

MARKING

DIAGRAM

128

The lowest TPD delay time results from terminating only one output

pair, and the greatest TPD delay time results from terminating all the

output pairs. This shift is about 10−20 pS in TPD. The skew between

any two output pairs within a device is typically about 25 nS. If other

output pairs are not terminated, the lowest TPD delay time results

from both output pairs and the skew is typically 25 nS. When all

outputs are terminated, the greatest TPD (delay time) occurs and all

outputs display about the same 10−20 pS increase in TPD, so the

relative skew between any two output pairs remains about 25 nS.

For more information on using PECL, designers should refer to

Application Note AN1406/D.

MC100E210FN

AWLYYWW

PLCC−28

FN SUFFIX

CASE 776

= Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

The V pin, an internally generated voltage supply, is available to this

device only. For single-ended input conditions, the unused differential

input is connected to V as a switching reference voltage. V may also

*For additional information, see Application Note

AND8002/D

rebias AC coupled inputs. When used, decouple V and V via a

0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When

not used, V should be left open.

• Dual Differential Fanout Buffers

ORDERING INFORMATION

• 200 ps Part−to−Part Skew

†

Device

Package

Shipping

• 50 ps Typical Output−to−Output Skew

• Low Voltage ECL/PECL Compatible

• The 100 Series Contains Temperature Compensation

• 28−lead PLCC Packaging

MC100E210FN

MC100E210FNR2

PLCC−28 37 Units / Rail

PLCC−28 500 Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

• PECL Mode Operating Range: V = 4.2 V to 5.7 V with V = 0 V

• NECL Mode Operating Range: V = 0 V with V = −4.2 V to −5.7 V

• Internal Input 75 KW Pulldown Resistors

• Q Output will Default LOW with Inputs Open or at V

• ESD Protection: Human Body Model; >2 KV,

Machine Model; >200 V

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

• Moisture Sensitivity Level 1

For Additional Information, see Application Note AND8003/D

• Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

• Transistor Count = 179 devices

Semiconductor Components Industries, LLC, 2003

Publication Order Number:

October, 2003 − Rev. 2

MC100E210/D

12 3 4 5 6 7 8

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与MC100E210相关器件

型号	品牌	获取价格	描述	数据表
MC100E210FN	ONSEMI	获取价格	Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer
MC100E210FN	MOTOROLA	获取价格	LOW VOLTAGE DUAL 1:4, 1:5 DIFFERENTIAL FANOUT BUFFER
MC100E210FNG	ONSEMI	获取价格	5.0 V ECL Dual 1:4, 1:5 Differential Clock/Data Fanout Buffer, 28 LEAD PLCC, 37-TUBE
MC100E210FNR2	ONSEMI	获取价格	Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer
MC100E210FNR2	MOTOROLA	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, PLASTI
MC100E210FNR2G	ONSEMI	获取价格	暂无描述
MC100E211	ONSEMI	获取价格	1:6 DIFFERENTIAL CLOCK DISTRIBUTION CHIP
MC100E211FN	MOTOROLA	获取价格	1:6 DIFFERENTIAL CLOCK DISTRIBUTION CHIP
MC100E211FN	ONSEMI	获取价格	5V ECL 1:6 Differential Clock Distribution Chip
MC100E211FNG	ONSEMI	获取价格	5V ECL 1:6 Differential Clock Distribution Chip

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