Order this document
by MC10E195/D
SEMICONDUCTOR TECHNICAL DATA
The MC10E/100E195 is a programmable delay chip (PDC) designed
primarily for clock de-skewing and timing adjustment. It provides variable
delay of a differential ECL input transition.
The delay section consists of a chain of gates organized as shown in
the logic symbol. The first two delay elements feature gates that have
been modified to have delays 1.25 and 1.5 times the basic gate delay of
approximately 80 ps. These two elements provide the E195 with a
digitally-selectable resolution of approximately 20 ps. The required
device delay is selected by the seven address inputs D[0:6], which are
latched on chip by a high signal on the latch enable (LEN) control.
PROGRAMMABLE
DELAY CHIP
Because the delay programmability of the E195 is achieved by purely
differential ECL gate delays the device will operate at frequencies of >1.0
GHz while maintaining over 600 mV of output swing.
The E195 thus offers very fine resolution, at very high frequencies, that
is selectable entirely from a digital input allowing for very accurate system
clock timing.
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
An eighth latched input, D7, is provided for cascading multiple PDC’s
for increased programmable range. The cascade logic allows full control
of multiple PDC’s, at the expense of only a single added line to the data
bus for each additional PDC, without the need for any external gating.
D2
D3
24
D4
23
D5
22
D6
21
D7
20
NC
• 2.0ns Worst Case Delay Range
• ≈20ps/Delay Step Resolution
• >1.0GHz Bandwidth
25
D1
19
NC 18
26
17
NC
27 D0
• On Chip Cascade Circuitry
• Extended 100E V
• 75KΩ Input Pulldown Resistors
Range of –4.2 to –5.46V
EE
V
16
15
28 LEN
CC
Pinout:
28-Lead PLCC
(Top View)
V
V
V
1
2
3
4
EE
CCO
PIN NAMES
Pin
IN
IN
V
Q 14
Q 13
12
Function
IN/IN
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE
Signal Input
Input Enable
Mux Select Inputs
Signal Output
Latch Enable
Min Delay Set
Max Delay Set
Cascade Signal
BB
CCO
5
6
7
8
9
10
11
NC
NC EN
LOGIC DIAGRAM – SIMPLIFIED
V
BB
1
1
0
0
0
0
0
0
0
IN
IN
4 GATES
8 GATES
16 GATES
1
1
1
1
1
1
1
1
1
1
0
Q
Q
EN
* 1.25
* 1.5
1
1
CASCADE
LEN
Q
LEN
SET MIN
SET MAX
7 BIT LATCH
LATCH
D
CASCADE
CASCADE
D0
* DELAYS ARE 25% OR 50% LONGER THAN
D1
D2
D3
D4
D5
D6
D7
* STANDARD (STANDARD
≈ 80 PS)
04/99
REV 3
2–1
Motorola, Inc. 1999