MC10E195, MC100E195
5VꢀECL Programmable
Delay Chip
Description
The MC10E/100E195 is a programmable delay chip (PDC)
designed primarily for clock de-skewing and timing adjustment. It
provides variable delay of a differential ECL input transition.
The delay section consists of a chain of gates organized as shown in
the logic symbol. The first two delay elements feature gates that have
been modified to have delays 1.25 and 1.5 times the basic gate delay of
approximately 80 ps. These two elements provide the E195 with a
digitally-selectable resolution of approximately 20 ps. The required
device delay is selected by the seven address inputs D[0:6], which are
latched on chip by a high signal on the latch enable (LEN) control.
Because the delay programmability of the E195 is achieved by
purely differential ECL gate delays the device will operate at
frequencies of > 1.0 GHz while maintaining over 600 mV of output
swing.
http://onsemi.com
PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE195FNG
AWLYYWW
The E195 thus offers very fine resolution, at very high frequencies,
that is selectable entirely from a digital input allowing for very
accurate system clock timing.
An eighth latched input, D7, is provided for cascading multiple
PDC’s for increased programmable range. The cascade logic allows
full control of multiple PDC’s, at the expense of only a single added
line to the data bus for each additional PDC, without the need for any
external gating.
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
The V pin, an internally generated voltage supply, is available to
BB
this device only. For single-ended input conditions, the unused
*For additional marking information, refer to
Application Note AND8002/D.
differential input is connected to V as a switching reference voltage.
BB
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
to 0.5 mA. When not used, V should be left open.
BB
The 100 Series contains temperature compensation.
Features
• 2.0 ns Worst Case Delay Range
• ≈20 ps/Delay Step Resolution
• >1.0 GHz Bandwidth
• On Chip Cascade Circuitry
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 368 devices
• PECL Mode Operating Range: V = 4.2 V to 5.7 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
with V = −4.2 V to −5.7 V
EE
• Pb−Free Packages are Available*
• Internal Input 50 kW Pulldown Resistors
• ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 10
MC10E195/D