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MC100E195FNR2G PDF预览

MC100E195FNR2G

更新时间: 2024-11-23 05:10:27
品牌 Logo 应用领域
安森美 - ONSEMI 延迟线
页数 文件大小 规格书
11页 151K
描述
5V ECL Programmable Delay Chip

MC100E195FNR2G 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCJ, LDCC28,.5SQ针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.13
Is Samacsys:NBase Number Matches:1

MC100E195FNR2G 数据手册

 浏览型号MC100E195FNR2G的Datasheet PDF文件第2页浏览型号MC100E195FNR2G的Datasheet PDF文件第3页浏览型号MC100E195FNR2G的Datasheet PDF文件第4页浏览型号MC100E195FNR2G的Datasheet PDF文件第5页浏览型号MC100E195FNR2G的Datasheet PDF文件第6页浏览型号MC100E195FNR2G的Datasheet PDF文件第7页 
MC10E195, MC100E195  
5VꢀECL Programmable  
Delay Chip  
Description  
The MC10E/100E195 is a programmable delay chip (PDC)  
designed primarily for clock de-skewing and timing adjustment. It  
provides variable delay of a differential ECL input transition.  
The delay section consists of a chain of gates organized as shown in  
the logic symbol. The first two delay elements feature gates that have  
been modified to have delays 1.25 and 1.5 times the basic gate delay of  
approximately 80 ps. These two elements provide the E195 with a  
digitally-selectable resolution of approximately 20 ps. The required  
device delay is selected by the seven address inputs D[0:6], which are  
latched on chip by a high signal on the latch enable (LEN) control.  
Because the delay programmability of the E195 is achieved by  
purely differential ECL gate delays the device will operate at  
frequencies of > 1.0 GHz while maintaining over 600 mV of output  
swing.  
http://onsemi.com  
PLCC28  
FN SUFFIX  
CASE 776  
MARKING DIAGRAM*  
1
MCxxxE195FNG  
AWLYYWW  
The E195 thus offers very fine resolution, at very high frequencies,  
that is selectable entirely from a digital input allowing for very  
accurate system clock timing.  
An eighth latched input, D7, is provided for cascading multiple  
PDC’s for increased programmable range. The cascade logic allows  
full control of multiple PDC’s, at the expense of only a single added  
line to the data bus for each additional PDC, without the need for any  
external gating.  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single-ended input conditions, the unused  
*For additional marking information, refer to  
Application Note AND8002/D.  
differential input is connected to V as a switching reference voltage.  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
to 0.5 mA. When not used, V should be left open.  
BB  
The 100 Series contains temperature compensation.  
Features  
2.0 ns Worst Case Delay Range  
20 ps/Delay Step Resolution  
>1.0 GHz Bandwidth  
On Chip Cascade Circuitry  
Meets or Exceeds JEDEC Spec EIA/JESD78 IC  
Latchup Test  
Moisture Sensitivity Level: Pb = 1; PbFree = 3  
For Additional Information, see Application Note  
AND8003/D  
Flammability Rating: UL 94 V0 @ 0.125 in,  
Oxygen Index: 28 to 34  
Transistor Count = 368 devices  
PECL Mode Operating Range: V = 4.2 V to 5.7 V  
CC  
with V = 0 V  
EE  
NECL Mode Operating Range: V = 0 V  
CC  
with V = 4.2 V to 5.7 V  
EE  
PbFree Packages are Available*  
Internal Input 50 kW Pulldown Resistors  
ESD Protection: Human Body Model; > 2 kV,  
Machine Model; > 200 V  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 Rev. 10  
MC10E195/D  

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