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MC-45D32DC721KF-C80 PDF预览

MC-45D32DC721KF-C80

更新时间： 2024-11-28 07:03:15
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率
页数 文件大小 规格书
16页 190K
描述
32 M-WORD BY 72-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE

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MC-45D32DC721KF-C80 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIMM包装说明：DIMM,
针数：184Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.36
风险等级：5.92Is Samacsys：N
访问模式：DUAL BANK PAGE BURST最长访问时间：0.8 ns
其他特性：AUTO/SELF REFRESHJESD-30 代码：R-XDMA-N184
内存密度：2415919104 bit内存集成电路类型：DDR DRAM MODULE
内存宽度：72功能数量：1
端口数量：1端子数量：184
字数：33554432 words字数代码：32000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：32MX72
封装主体材料：UNSPECIFIED封装代码：DIMM
封装形状：RECTANGULAR封装形式：MICROELECTRONIC ASSEMBLY
认证状态：Not Qualified自我刷新：YES
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子形式：NO LEAD端子位置：DUAL
Base Number Matches：1

MC-45D32DC721KF-C80 数据手册

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PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
MC-45D32DC721  
32 M-WORD BY 72-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE  
REGISTERED TYPE  
Description  
The MC-45D32DC721 is a 33,554,432 words by 72 bits DDR synchronous dynamic RAM module on which 18  
pieces of 128M DDR SDRAM: µPD45D128842 are assembled.  
These modules provide high density and large quantities of memory in a small space without utilizing the surface-  
mounting technology on the printed circuit board.  
Decoupling capacitors are mounted on power supply line for noise reduction.  
Features  
• 33,554,432 words by 72 bits organization (ECC type)  
• Clock frequency  
Part number  
/CAS latency  
Clock frequency  
(MAX.)  
Module type  
MC-45D32DC721KF-C75  
MC-45D32DC721KF-C80  
MC-45D32DC721KFA-C75  
MC-45D32DC721KFA-C80  
CL = 2.5  
CL = 2  
133 MHz  
100 MHz  
125 MHz  
100 MHz  
133 MHz  
100 MHz  
125 MHz  
100 MHz  
DDR Registered DIMM  
Design specification Rev. 0.6 compliant  
CL = 2.5  
CL = 2  
CL = 2.5  
CL = 2  
DDR Registered DIMM  
Design specification Rev. 0.9 compliant  
CL = 2.5  
CL = 2  
• Fully Synchronous Dynamic RAM with all signals except DM, DQS and DQ referenced to a positive clock edge  
• Double Data Rate interface  
Differential CLK (/CLK) input  
Data inputs and DM are synchronized with both edges of DQS  
Data outputs and DQS are synchronized with a cross point of CLK and /CLK  
• Quad internal banks operation  
• Possible to assert random column address in every clock cycle  
• Programmable Mode register set  
/CAS latency (2, 2.5)  
Burst length (2, 4, 8)  
Wrap sequence (Sequential / Interleave)  
• Automatic precharge and controlled precharge  
• CBR (Auto) refresh and self refresh  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for  
availability and additional information.  
Document No. E0036N10 (1st edition)  
(Previous No. M14790EJ3V0DS00)  
Date Published January 2001 CP (K)  
Printed in Japan  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  
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MC-45V16AD641KF-A75 NEC

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