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MC-45V8AD641ES-A75

更新时间： 2024-11-06 20:41:39
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟动态存储器光电二极管内存集成电路
页数 文件大小 规格书
16页 245K
描述
MEMORY MODULE,SDRAM,VIRTUAL CHANNEL,8MX64,CMOS,DIMM,144PIN,PLASTIC

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中文翻译

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MC-45V8AD641ES-A75 技术参数

生命周期：Obsolete包装说明：DIMM, DIMM144,32
Reach Compliance Code：unknown风险等级：5.84
最长访问时间：5.4 ns最大时钟频率 (fCLK)：133 MHz
I/O 类型：COMMONJESD-30 代码：R-PDMA-N144
内存密度：536870912 bit内存集成电路类型：SYNCHRONOUS DRAM MODULE
内存宽度：64端子数量：144
字数：8388608 words字数代码：8000000
最高工作温度：70 °C最低工作温度：
组织：8MX64输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：DIMM
封装等效代码：DIMM144,32封装形状：RECTANGULAR
封装形式：MICROELECTRONIC ASSEMBLY电源：3.3 V
认证状态：Not Qualified刷新周期：4096
最大待机电流：0.004 A子类别：DRAMs
最大压摆率：0.64 mA标称供电电压 (Vsup)：3.3 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子形式：NO LEAD
端子节距：0.8 mm端子位置：DUAL
Base Number Matches：1

MC-45V8AD641ES-A75 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
MC-45V8AD641KS, 45V8AD641ES  
8M-WORD BY 64-BIT  
VirtualChannelTM SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)  
Description  
The MC-45V8AD641KS, 45V8AD641ES is a 8,388,608 words by 64 bits VirtualChannel synchronous dynamic RAM  
module (small outline DIMM) on which 8 pieces of 64M VirtualChannel SDRAM : µPD4565161 are assembled.  
This module provides high density and large quantities of memory in a small space without utilizing the surface-  
mounting technology on the printed circuit board.  
Decoupling capacitors are mounted on power supply line for noise reduction.  
Features  
• 8,388,608 words by 64 bits organization  
• Clock frequency and access time from CLK  
Part number  
Clock  
Access  
time  
Maximum supply current  
Operating  
Read  
latency frequency  
(MAX.)  
Refresh  
from CLK  
(MAX.)  
Channel  
read / write  
(Burst)  
Prefetch  
Restore  
Auto  
Self  
MC-45V8AD641KS-A75  
MC-45V8AD641KS-A10  
MC-45V8AD641KS-A15  
MC-45V8AD641ES-A75  
MC-45V8AD641ES-A10  
MC-45V8AD641ES-A15  
2
133 MHz  
100 MHz  
67 MHz  
5.4 ns  
6 ns  
440 mA  
480 mA  
400 mA  
340 mA  
480 mA  
400 mA  
340 mA  
640 mA  
560 mA  
540 mA  
640 mA  
560 mA  
540 mA  
8 mA  
420 mA  
380 mA  
440 mA  
420 mA  
380 mA  
1
2
12 ns  
5.4 ns  
6 ns  
133 MHz  
100 MHz  
67 MHz  
•
•
•
1
12 ns  
• Fully Standard Synchronous Dynamic RAM, with all signals referenced to a positive clock edge  
• Dual internal banks controlled by BA0 (Bank Select)  
• Programmable Wrap sequence (Sequential / Interleave)  
• Programmable burst length (1, 2, 4, 8 and 16)  
• Prefetch Read latency (4)  
• Auto precharge and without auto precharge  
• Auto refresh and Self refresh  
• Single 3.3 V ± 0.3 V power supply  
• Interface: LVTTL  
• Refresh cycle: 4K cycles / 64 ms  
• 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)  
• Unbuffered type  
• Serial PD  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. M13836EJ5V0DS00 (5th edition)  
Date Published December 1999 NS CP (K)  
Printed in Japan  
The mark • shows major revised points.  
1998  
©
1234567...16

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