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MC-45V8AB642KS-A75 PDF预览

MC-45V8AB642KS-A75

更新时间: 2024-11-06 11:11:11
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器时钟
页数 文件大小 规格书
16页 144K
描述
8M-WORD BY 64-BIT VirtualChannelTM DYNAMIC RAM MODULE (SO DIMM)

MC-45V8AB642KS-A75 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:MODULE包装说明:DIMM, DIMM144,32
针数:144Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.28
风险等级:5.92访问模式:DUAL BANK PAGE BURST
最长访问时间:5.4 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N144内存密度:536870912 bit
内存集成电路类型:SYNCHRONOUS DRAM MODULE内存宽度:64
湿度敏感等级:1功能数量:1
端口数量:1端子数量:144
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8MX64
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM144,32
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified刷新周期:4096
自我刷新:YES最大待机电流:0.0048 A
子类别:DRAMs最大压摆率:0.92 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:MOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

MC-45V8AB642KS-A75 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
MC-45V8AB642KS  
8M-WORD BY 64-BIT  
VirtualChannelTM DYNAMIC RAM MODULE (SO DIMM)  
Description  
The MC-45V8AB642KS is a 8,388,608 words by 64 bits VirtualChannel dynamic RAM module (small outline DIMM)  
on which 4 pieces of 128M VirtualChannel DRAM : µPD45V128161 are assembled.  
This module provides high density and large quantities of memory in a small space without utilizing the surface-  
mounting technology on the printed circuit board.  
Decoupling capacitors are mounted on power supply line for noise reduction.  
Features  
8,388,608 words by 64 bits organization  
Clock frequency and access time from CLK  
Part number  
Read  
Clock  
Access time  
from CLK  
Maximum supply current mA  
Operating  
latency  
frequency  
MHz (MAX.)  
Refresh  
Auto  
ns (MAX.)  
Prefetch Restore  
Channel  
Self  
read / write (Burst)  
MC-45V8AB642KS-A75  
2
133  
5.4  
600  
300  
920  
8
Fully Standard Synchronous Dynamic RAM, with all signals referenced to a positive clock edge  
Dual internal banks controlled by BA0 (Bank Select)  
Programmable wrap sequence (interleave)  
Programmable burst length (4)  
Read latency (2)  
Prefetch read latency (4)  
Auto precharge and without auto precharge  
Auto refresh and self refresh  
Single 3.3 V ± 0.3 V power supply  
Interface: LVTTL  
Refresh cycle: 4K cycles/64 ms  
144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)  
Unbuffered type  
Serial PD  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for  
availability and additional information.  
Document No. E0028N11 (Ver. 1.1)  
This Product became EOL in January, 2003.  
(Previous No. M15239EJ1V0DS00)  
Date Published April 2001 CP (K)  
Printed in Japan  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  

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