IS66/67WVE2M16EALL/BLL/CLL
32Mb Async/Page PSRAM
PRELIMINARY INFORMATION
Overview
The IS66/67WVE2M16EALL/BLL/CLL is an integrated memory device containing 32Mbit Pseudo Static
Random Access Memory using a self-refresh DRAM array organized as 2M words by 16 bits. The device
includes several power saving modes : Partial Array Refresh mode where data is retained in a portion of
the array and Deep Power Down mode. Both these modes reduce standby current drain. The die has
separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device
core.
Features
Asynchronous and page mode interface
Dual voltage rails for optional performance
Low Power Feature
Temperature Controlled Refresh
Partial Array Refresh
Deep power-down (DPD) mode
Operating temperature Range
ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V
BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V
CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V
Page mode read access
Interpage Read access : 55ns, 70ns
Intrapage Read access : 20ns
Low Power Consumption
Asynchronous Operation < 30 mA
Intrapage Read < 23mA
Standby < 180 µA (max.)
Deep power-down (DPD)
ALL/CLL: < 3µA (Typ)
Industrial: -40°C~85°C
Automotive A1: -40°C~85°C
Package:
48-ball TFBGA
BLL: < 10µA (Typ)
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products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
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c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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Rev. 0D | November 2014