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IS66WVH8M8BLL-100B1LI PDF预览

IS66WVH8M8BLL-100B1LI

更新时间： 2024-11-14 21:10:03
品牌 Logo 应用领域
美国芯成 - ISSI 内存集成电路
页数 文件大小 规格书
65页 2344K
描述
Pseudo Static RAM, 8MX8, CMOS, PBGA24, 6 X 8 MM, 1.20 MM HEIGHT, LEAD FREE, MO-207, TFBGA-24

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IS66WVH8M8BLL-100B1LI 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TFBGA-24Reach Compliance Code：compliant
Factory Lead Time：10 weeks风险等级：2.28
JESD-30 代码：R-PBGA-B24长度：8 mm
内存密度：67108864 bit内存集成电路类型：PSEUDO STATIC RAM
内存宽度：8功能数量：1
端子数量：24字数：8388608 words
字数代码：8000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：8MX8封装主体材料：PLASTIC/EPOXY
封装代码：TBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6 mmBase Number Matches：1

IS66WVH8M8BLL-100B1LI 数据手册

 浏览型号IS66WVH8M8BLL-100B1LI的Datasheet PDF文件第2页浏览型号IS66WVH8M8BLL-100B1LI的Datasheet PDF文件第3页浏览型号IS66WVH8M8BLL-100B1LI的Datasheet PDF文件第4页浏览型号IS66WVH8M8BLL-100B1LI的Datasheet PDF文件第5页浏览型号IS66WVH8M8BLL-100B1LI的Datasheet PDF文件第6页浏览型号IS66WVH8M8BLL-100B1LI的Datasheet PDF文件第7页 
IS66WVH8M8ALL/BLL  
IS67WVH8M8ALL/BLL  
8M x 8 HyperRAM™  
AUGUST 2016  
Overview  
The IS66/67WVH8M8ALL/BLL are integrated memory device containing 64Mbit Pseudo Static Random  
Access Memory using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports a  
HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden  
Refresh Operation, and Automotive Temperature Operation, designed specially for Mobile and  
Automotive applications.  
Distinctive Characteristics  
HyperBusTM Low Signal Count Interface  
3.0V I/O, 11 bus signals  
High Performance  
– Single ended clock (CK)  
Up to 333MB/s  
1.8V I/O, 12 bus signals  
Double-Data Rate (DDR) - two data transfers per clock  
166-MHz clock rate (333 MB/s) at 1.8V VCC  
100-MHz clock rate (200 MB/s) at 3.0V VCC  
Sequential burst transactions  
– Differential clock (CK, CK#)  
Chip Select (CS#)  
8-bit data bus (DQ[7:0])  
Read-Write Data Strobe (RWDS)  
Configurable Burst Characteristics  
– Wrapped burst lengths:  
– Bidirectional Data Strobe / Mask  
– Output at the start of all transactions to indicate refresh latency  
– Output during read transactions as Read Data Strobe  
– Input during write transactions as Write Data Mask  
– 16 bytes (8 clocks)  
– 32 bytes (16 clocks)  
– 64 bytes (32 clocks)  
– 128 bytes (64 clocks)  
– Linear burst  
RESET#  
V
– Hybrid option - one wrapped burst followed by linear burst  
– Wrapped or linear burst type selected in each transaction  
– Configurable output drive strength  
CC  
V
Q
CC  
CS#  
CK  
DQ[7:0]  
RWDS  
Package and Die Options  
– 25-ball FBGA footprint  
CK#  
– 24-ball FBGA footprint  
V
SS  
V
Q
SS  
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI  
assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device  
specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be  
expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated  
Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev.A  
1
06/28/2016  
1234567...65

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