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IS67WVE4M16BLL-70BLA1-TR PDF预览

IS67WVE4M16BLL-70BLA1-TR

更新时间: 2024-11-14 19:57:43
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
30页 524K
描述
Application Specific SRAM, 4MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, LEAD FREE, MO-207, TFBGA-48

IS67WVE4M16BLL-70BLA1-TR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:TFBGA, BGA48,6X8,30
Reach Compliance Code:compliant风险等级:5.67
最长访问时间:70 nsI/O 类型:COMMON
JESD-30 代码:R-PBGA-B48JESD-609代码:e3
长度:8 mm内存密度:67108864 bit
内存集成电路类型:APPLICATION SPECIFIC SRAM内存宽度:16
湿度敏感等级:1功能数量:1
端子数量:48字数:4194304 words
字数代码:4000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:4MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA48,6X8,30封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:3/3.3 V
认证状态:Not Qualified筛选级别:AEC-Q100
座面最大高度:1.2 mm最大待机电流:0.00001 A
子类别:Other Memory ICs最大压摆率:0.03 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6 mm
Base Number Matches:1

IS67WVE4M16BLL-70BLA1-TR 数据手册

 浏览型号IS67WVE4M16BLL-70BLA1-TR的Datasheet PDF文件第2页浏览型号IS67WVE4M16BLL-70BLA1-TR的Datasheet PDF文件第3页浏览型号IS67WVE4M16BLL-70BLA1-TR的Datasheet PDF文件第4页浏览型号IS67WVE4M16BLL-70BLA1-TR的Datasheet PDF文件第5页浏览型号IS67WVE4M16BLL-70BLA1-TR的Datasheet PDF文件第6页浏览型号IS67WVE4M16BLL-70BLA1-TR的Datasheet PDF文件第7页 
IS66WVE4M16BLL  
3.0V Core Async/Page PSRAM  
Overview  
The IS66WVE4M16BLL is an integrated memory device containing 64Mbit Pseudo Static Random Access  
Memory using a self-refresh DRAM array organized as 4M words by 16 bits. The device includes several  
power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and  
Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power  
rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.  
Features  
Asynchronous and page mode interface  
Dual voltage rails for optional performance  
VDD 2.7V~3.6V, VDDQ 2.7V~3.6V  
Page mode read access  
Interpage Read access : 70ns  
Intrapage Read access : 20ns  
Low Power Consumption  
Low Power Feature  
Temperature Controlled Refresh  
Partial Array Refresh  
Deep power-down (DPD) mode  
Operating temperature Range  
Industrial -40°C~85°C  
Packages:  
48-ball TFBGA, 48-pin TSOP-I  
Asynchronous Operation < 30 mA  
Intrapage Read < 18mA  
Standby < 180 uA (max.)  
Deep power-down (DPD) < 3uA (Typ)  
Notes:  
1. The 48-pin TSOP-I package option is not yet available. Please contact SRAM Marketing at sram@issi.com  
for additional information.  
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its  
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services  
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information  
and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or  
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or  
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to  
its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
1
www.issi.com - SRAM@issi.com  
Rev.A | May 2011  

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