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IS67WVE4M16TCLL-70BLA1 PDF预览

IS67WVE4M16TCLL-70BLA1

更新时间: 2024-11-14 19:49:43
品牌 Logo 应用领域
美国芯成 - ISSI 内存集成电路
页数 文件大小 规格书
34页 684K
描述
Pseudo Static RAM, 4MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, LEAD FREE, MO-207, TFBGA-48

IS67WVE4M16TCLL-70BLA1 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TFBGA, BGA48,6X8,30Reach Compliance Code:compliant
HTS代码:8542.32.00.41风险等级:5.76
最长访问时间:70 nsI/O 类型:COMMON
JESD-30 代码:R-PBGA-B48JESD-609代码:e1
长度:8 mm内存密度:67108864 bit
内存集成电路类型:PSEUDO STATIC RAM内存宽度:16
功能数量:1端口数量:1
端子数量:48字数:4194304 words
字数代码:4000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:4MX16输出特性:3-STATE
可输出:NO封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装等效代码:BGA48,6X8,30
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
反向引出线:NO筛选级别:AEC-Q100
座面最大高度:1.2 mm最大待机电流:0.00015 A
最小待机电流:1.7 V最大压摆率:0.025 mA
最大供电电压 (Vsup):1.95 V最小供电电压 (Vsup):1.7 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:0.75 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:10
宽度:6 mmBase Number Matches:1

IS67WVE4M16TCLL-70BLA1 数据手册

 浏览型号IS67WVE4M16TCLL-70BLA1的Datasheet PDF文件第2页浏览型号IS67WVE4M16TCLL-70BLA1的Datasheet PDF文件第3页浏览型号IS67WVE4M16TCLL-70BLA1的Datasheet PDF文件第4页浏览型号IS67WVE4M16TCLL-70BLA1的Datasheet PDF文件第5页浏览型号IS67WVE4M16TCLL-70BLA1的Datasheet PDF文件第6页浏览型号IS67WVE4M16TCLL-70BLA1的Datasheet PDF文件第7页 
IS66/67WVE4M16EALL/EBLL/ECLL  
IS66/67WVE4M16TALL/TBLL/TCLL  
64Mb Async/Page PSRAM  
NOVEMBER 2015  
Overview  
The IS66/67WVE4M16EALL/BLL/CLL and IS66/67WVE4M16TALL/BLL/CLL integrated memory device  
containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 4M  
words by 16 bits. The device includes several power saving modes : Partial Array Refresh mode where  
data is retained in a portion of the array and Deep Power Down mode. Both these modes reduce standby  
current drain. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate  
power supply from the device core.  
Features  
Asynchronous and page mode interface  
Dual voltage rails for optional performance  
Low Power Feature  
Temperature Controlled Refresh  
Partial Array Refresh  
Deep power-down (DPD) mode  
Operating temperature Range  
ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V  
BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V  
CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V  
Page mode read access  
Interpage Read access : 60ns, 70ns  
Intrapage Read access : 25ns  
Low Power Consumption  
Asynchronous Operation < 30 mA  
Intrapage Read < 23mA  
Standby < 200 uA (max.)  
Deep power-down (DPD)  
ALL/CLL: < 3µA (Typ)  
Industrial: -40°C~85°C  
Automotive A1: -40°C~85°C  
Packages:  
48-ball TFBGA  
BLL: < 10µA (Typ)  
Notes:  
1. The 48-pin TSOP-I package option is not yet available. Please contact SRAM Marketing at sram@issi.com  
for additional information.  
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its  
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services  
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information  
and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or  
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or  
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to  
its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
1
Rev. D | Oct. 2015  
www.issi.com - SRAM@issi.com  

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