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IS67WV51216DBLL-70TLA1 PDF预览

IS67WV51216DBLL-70TLA1

更新时间： 2024-02-18 06:34:39
品牌 Logo 应用领域
美国芯成 - ISSI 光电二极管内存集成电路
页数 文件大小 规格书
17页 463K
描述
Pseudo Static RAM, 512KX16, 70ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, TSOP2-44

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IS67WV51216DBLL-70TLA1 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：TSOP2, TSOP44,.46,32
Reach Compliance Code：compliant风险等级：5.58
最长访问时间：70 nsI/O 类型：COMMON
JESD-30 代码：R-PDSO-G44JESD-609代码：e3
长度：18.41 mm内存密度：8388608 bit
内存集成电路类型：APPLICATION SPECIFIC SRAM内存宽度：16
湿度敏感等级：1功能数量：1
端子数量：44字数：524288 words
字数代码：512000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装等效代码：TSOP44,.46,32封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：225电源：3/3.3 V
认证状态：Not Qualified筛选级别：AEC-Q100
座面最大高度：1.2 mm最大待机电流：0.00015 A
子类别：Other Memory ICs最大压摆率：0.035 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.5 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：10.16 mm
Base Number Matches：1

IS67WV51216DBLL-70TLA1 数据手册

 浏览型号IS67WV51216DBLL-70TLA1的Datasheet PDF文件第2页浏览型号IS67WV51216DBLL-70TLA1的Datasheet PDF文件第3页浏览型号IS67WV51216DBLL-70TLA1的Datasheet PDF文件第4页浏览型号IS67WV51216DBLL-70TLA1的Datasheet PDF文件第5页浏览型号IS67WV51216DBLL-70TLA1的Datasheet PDF文件第6页浏览型号IS67WV51216DBLL-70TLA1的Datasheet PDF文件第7页 
            
            
            
             
             
IS66WV51216DALL  
IS66/67WV51216DBLL  
JULYꢀ2011  
8MbꢀLOWꢀVOLTAGE,ꢀ  
ULTRAꢀLOWꢀPOWERꢀPSEUDOꢀCMOSꢀSTATICꢀRAMꢀ  
ꢀꢀꢀꢀꢀꢀ  
FEATURES  
DESCRIPTION  
• High-speed access time:  
TheISSIIS66WV51216DALLandIS66/67WV51216DBLL  
are high-speed, 8M bit static RAMs organized as 512K  
words by 16 bits. It is fabricated using ISSI's high-  
performanceCMOStechnology.Thishighlyreliableprocess  
coupled with innovative circuit design techniques, yields  
high-performance and low power consumption devices.  
– 70ns (IS66WV51216DALL, IS66/67WV51216DBLL)  
– 55ns (IS66/67WV51216DBLL)  
• CMOS low power operation  
• Single power supply  
– Vdd = 1.7V-1.95V (IS66WV51216dALL)  
– Vdd = 2.5V-3.6V (IS66/67WV51216dBLL)  
• Three state outputs  
When CS1 is HIGH (deselected) or when CS2 is LOW  
(deselected) or when CS1 is LOW, CS2 is HIGH and both  
LBandUBareHIGH, thedeviceassumesastandbymode  
at which the power dissipation can be reduced down with  
CMOS input levels.  
• Data control for upper and lower bytes  
• Industrial temperature available  
• Lead-free available  
Easy memory expansion is provided by using Chip Enable  
and Output Enable inputs. The active LOW Write Enable  
(WE) controls both writing and reading of the memory. A  
data byte allows Upper Byte (UB) and Lower Byte (LB)  
access.  
The IS66WV51216DALL and IS66/67WV51216DBLL are  
packaged in the JEDEC standard 48-ball mini BGA (6mm  
x 8mm) and 44-Pin TSOP (TYPE II). The device is aslo  
available for die sales.  
FUNCTIONALꢀBLOCKꢀDIAGRAM  
512K x 16  
MEMORY ARRAY  
A0-A18  
DECODER  
V
DD  
GND  
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
COLUMN I/O  
CIRCUIT  
I/O8-I/O15  
Upper Byte  
CS2  
CS1  
OE  
CONTROL  
CIRCUIT  
WE  
UB  
LB  
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause  
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written  
assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev.ꢀ A  
06/28/2011  
1234567...17

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