Datasheet > 存储 > SRAM> IS61NLF12836A-6.5TQI

IS61NLF12836A-6.5TQI

更新时间： 2024-09-14 02:54:51

品牌	Logo	应用领域
美国芯成 - ISSI		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
27页	194K
描述
128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM

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IS61NLF12836A-6.5TQI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	TQFP-100	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.79
Is Samacsys：	N	最长访问时间：	6.5 ns
其他特性：	FLOW-THROUGH ARCHITECTURE	最大时钟频率 (fCLK)：	133 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0	长度：	20 mm
内存密度：	4718592 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	36	功能数量：	1
端子数量：	100	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	128KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.035 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.18 mA
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

IS61NLF12836A-6.5TQI 数据手册

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IS61NLF12836A/IS61NVF12836A

IS61NLF25618A/IS61NVF25618A

ISSI

PRELIMINARY INFORMATION

SEPTEMBER 2005

128K x 36 and 256K x 18

4Mb, FLOW THROUGH 'NO WAIT'

STATE BUS SRAM

FEATURES

DESCRIPTION

The 4 Meg 'NLF/NVF' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organized as 128K words by 36 bits and 256K words by 18

bits, fabricated with ISSI's advanced CMOS technology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single Read/Write control pin

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control using

MODE input

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

• JEDEC 100-pin TQFP, 119-ball PBGA, and 165-

ball PBGA packages

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be written.

• Power supply:

NVF: V^DD2.5V (± 5%), VDDQ 2.5V (± 5%)

NLF: V^DD3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)

A burst mode pin (MODE) defines the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

• Industrial temperature available

• Lead-free available

FAST ACCESS TIME

Symbol

tKQ

Parameter

6.5

7.5

133

7.5

8.5

117

Units

Clock Access Time

Cycle Time

tKC

Frequency

MHz

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. 00A

08/26/05

12 3 4 5 6 7...27

中文翻译

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与IS61NLF12836A-6.5TQI相关器件

型号	品牌	获取价格	描述	数据表
IS61NLF12836A-7.5B2	ISSI	获取价格	128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF12836A-7.5B2I	ISSI	获取价格	128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF12836A-7.5B3	ISSI	获取价格	128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF12836A-7.5B3I	ISSI	获取价格	128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF12836A-7.5TQ	ISSI	获取价格	128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF12836A-7.5TQI	ISSI	获取价格	128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF12836A-7.5TQLI	ISSI	获取价格	128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF12836EC-7.5TQLI	ISSI	获取价格	IC SRAM 4.5M PARALLEL 100LQFP
IS61NLF12836EC-7.5TQLI-TR	ISSI	获取价格	IC SRAM 4.5M PARALLEL 100LQFP
IS61NLF204818A	ISSI	获取价格	STATE BUS SRAM

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