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IS61NLF12836A-7.5TQLI

更新时间： 2024-11-26 04:44:47

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
27页	194K
描述
128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM

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IS61NLF12836A/IS61NVF12836A

IS61NLF25618A/IS61NVF25618A

ISSI

PRELIMINARY INFORMATION

SEPTEMBER 2005

128K x 36 and 256K x 18

4Mb, FLOW THROUGH 'NO WAIT'

STATE BUS SRAM

FEATURES

DESCRIPTION

The 4 Meg 'NLF/NVF' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organized as 128K words by 36 bits and 256K words by 18

bits, fabricated with ISSI's advanced CMOS technology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single Read/Write control pin

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control using

MODE input

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

• JEDEC 100-pin TQFP, 119-ball PBGA, and 165-

ball PBGA packages

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be written.

• Power supply:

NVF: V^DD2.5V (± 5%), VDDQ 2.5V (± 5%)

NLF: V^DD3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)

A burst mode pin (MODE) defines the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

• Industrial temperature available

• Lead-free available

FAST ACCESS TIME

Symbol

tKQ

Parameter

6.5

7.5

133

7.5

8.5

117

Units

Clock Access Time

Cycle Time

tKC

Frequency

MHz

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. 00A

08/26/05

12 3 4 5 6 7...27

中文翻译

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IS61NLF12836A-7.5TQLI 替代型号

型号	品牌	替代类型	描述	数据表
IS61NLF12836A-7.5TQI	ISSI	完全替代	128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
CY7C1351G-133AXC	CYPRESS	功能相似	4-Mbit (128K x 36) Flow-through SRAM with NoB

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IS61NLF12836EC-7.5TQLI-TR	ISSI	获取价格	IC SRAM 4.5M PARALLEL 100LQFP
IS61NLF204818A	ISSI	获取价格	STATE BUS SRAM
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IS61NLF204818A-6.5TQ	ISSI	获取价格	STATE BUS SRAM
IS61NLF204818A-6.5TQI	ISSI	获取价格	STATE BUS SRAM
IS61NLF204818A-7.5B3	ISSI	获取价格	STATE BUS SRAM
IS61NLF204818A-7.5B3I	ISSI	获取价格	STATE BUS SRAM
IS61NLF204818A-7.5TQ	ISSI	获取价格	STATE BUS SRAM

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