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IS61NLF204818A-7.5TQLI PDF预览

IS61NLF204818A-7.5TQLI

更新时间: 2024-09-16 09:51:51
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器
页数 文件大小 规格书
18页 287K
描述
ZBT SRAM, 2MX18, 7.5ns, CMOS, PQFP100, TQFP-100

IS61NLF204818A-7.5TQLI 数据手册

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IS61NLF102436A/IS61NVF102436A  
IS61NLF204818A/IS61NVF204818Aꢀ  
1Mꢀxꢀ36ꢀandꢀ2Mꢀxꢀ18  
36Mb,ꢀFLOWTHROUGHꢀ'NOꢀWAIT'ꢀ  
STATEꢀBUSꢀSRAM  
FEBRUARYꢀ2012  
DESCRIPTION  
FEATURES  
Theꢀ36ꢀMegꢀ'NLF/NVF'ꢀproductꢀfamilyꢀfeatureꢀhigh-speed,ꢀ  
low-powerꢀsynchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀ  
aꢀburstable,ꢀhigh-performance,ꢀ'noꢀwait'ꢀstate,ꢀdeviceꢀforꢀ  
networkingandcommunicationsapplications.Theyareꢀ  
organizedꢀasꢀ1Mꢀwordsꢀbyꢀ36ꢀbitsꢀandꢀ2Mꢀꢀwordsꢀbyꢀ18ꢀ  
bits,ꢀfabricatedꢀwithꢀISSI'sꢀadvancedꢀCMOSꢀtechnology.  
•ꢀ 100ꢀpercentꢀbusꢀutilization  
•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite  
•ꢀ Internalꢀself-timedꢀwriteꢀcycle  
•ꢀ IndividualꢀByteꢀWriteꢀControl  
•ꢀ SingleꢀRead/Writeꢀcontrolꢀpin  
Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ  
eliminatedꢀwhenꢀtheꢀbusꢀswitchesꢀfromꢀreadꢀtoꢀwrite,ꢀorꢀ  
writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ  
high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ  
intoꢀaꢀsingleꢀmonolithicꢀcircuit.  
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ  
dataꢀandꢀcontrol  
•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-  
ingꢀMODEꢀinputꢀ  
Allsynchronousinputspassthroughregistersarecontrolledꢀ  
byapositive-edge-triggeredsingleclockinput.Operationsꢀ  
maybesuspendedandallsynchronousinputsignoredꢀ  
whenꢀClockꢀEnable,ꢀCKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ  
deviceꢀwillꢀholdꢀtheirꢀpreviousꢀvalues.  
•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ  
andꢀaddressꢀpipelining  
•ꢀ PowerꢀDownꢀmode  
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs  
•ꢀ CKEꢀpinꢀtoꢀenableꢀclockꢀandꢀsuspendꢀoperation  
•ꢀ JEDECꢀ100-pinꢀTQFPꢀpackage  
AllRead,WriteandDeselectcyclesareinitiatedbytheADVꢀ  
input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ  
isincremented.Newexternaladdressescanbeloadedꢀ  
whenꢀADVꢀisꢀLOW.  
•ꢀ Powerꢀsupply:ꢀ  
Writeꢀ cyclesꢀ areꢀ internallyꢀ self-timedꢀ andꢀ areꢀ initiatedꢀ  
bytherisingedgeoftheclockinputsandwhenWEisꢀ  
LOW.ꢀSeparateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀ  
written.  
NVF:ꢀVdd 2.5Vꢀ( ꢀ5%),ꢀVddqꢀ2.5Vꢀ( ꢀ5%)  
NLF:ꢀVddꢀ3.3Vꢀ( ꢀ5%),ꢀVddqꢀ3.3V/2.5Vꢀ( ꢀ5%)  
•ꢀ Industrialꢀtemperatureꢀavailable  
•ꢀ Lead-freeꢀavailable  
ꢀAꢀburstꢀmodeꢀpinꢀ(MODE)ꢀdefinesꢀtheꢀorderꢀofꢀtheꢀburstꢀ  
sequence.WhentiedHIGH,theinterleavedburstsequenceꢀ  
isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ  
selected.  
FASTꢀACCESSꢀTIME  
Symbolꢀ  
Parameterꢀ  
6.5ꢀ  
6.5ꢀ  
7.5ꢀ  
133ꢀ  
7.5ꢀ  
7.5ꢀ  
8.5ꢀ  
117ꢀ  
Units  
ns  
tkqꢀ  
tkcꢀ  
ClockꢀAccessꢀTimeꢀ  
CycleꢀTimeꢀ  
ns  
Frequencyꢀ  
MHz  
Copyrightꢀ©ꢀ2011ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀAllꢀrightsꢀreserved.ꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀnotice.ꢀISSIꢀassumesꢀnoꢀ  
liabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlatestꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀ  
anyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.  
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀ  
failureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀunlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀ  
assuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:  
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;  
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand  
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ  
1
Rev.ꢀ Cꢀ  
02/12/2012  

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