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IS61NLF204818A-7.5B3 PDF预览

IS61NLF204818A-7.5B3

更新时间： 2024-11-24 05:39:35
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
23页 364K
描述
STATE BUS SRAM

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中文翻译

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IS61NLF204818A-7.5B3 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：TBGA, BGA165,11X15,40针数：165
Reach Compliance Code：not_compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.83
Is Samacsys：N最长访问时间：7.5 ns
最大时钟频率 (fCLK)：117 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e0
长度：15 mm内存密度：37748736 bit
内存集成电路类型：ZBT SRAM内存宽度：18
功能数量：1端子数量：165
字数：2097152 words字数代码：2000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：2MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.2 mm最大待机电流：0.1 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.375 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：13 mmBase Number Matches：1

IS61NLF204818A-7.5B3 数据手册

 浏览型号IS61NLF204818A-7.5B3的Datasheet PDF文件第2页浏览型号IS61NLF204818A-7.5B3的Datasheet PDF文件第3页浏览型号IS61NLF204818A-7.5B3的Datasheet PDF文件第4页浏览型号IS61NLF204818A-7.5B3的Datasheet PDF文件第5页浏览型号IS61NLF204818A-7.5B3的Datasheet PDF文件第6页浏览型号IS61NLF204818A-7.5B3的Datasheet PDF文件第7页 
IS61NLF102436A/IS61NVF102436A  
IS61NLF204818A/IS61NVF204818A  
1M x 36 and 2M x 18  
36Mb, FLOW THROUGH 'NO WAIT'  
STATE BUS SRAM  
JUNE 2008  
DESCRIPTION  
FEATURES  
Theꢀ36ꢀMegꢀ'NLF/NVF'ꢀproductꢀfamilyꢀfeatureꢀhigh-speed,ꢀ  
low-powerꢀsynchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀ  
aꢀburstable,ꢀhigh-performance,ꢀ'noꢀwait'ꢀstate,ꢀdeviceꢀforꢀ  
networkingꢀandꢀcommunicationsꢀapplications.ꢀTheyꢀareꢀ  
organizedꢀasꢀ1Mꢀwordsꢀbyꢀ36ꢀbitsꢀandꢀ2Mꢀꢀwordsꢀbyꢀ18ꢀ  
bits, fabricated with ISSI'sꢀadvancedꢀCMOSꢀtechnology.  
•ꢀ 100ꢀpercentꢀbusꢀutilization  
•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite  
•ꢀ Internalꢀself-timedꢀwriteꢀcycle  
•ꢀ IndividualꢀByteꢀWriteꢀControl  
•ꢀ SingleꢀRead/Writeꢀcontrolꢀpin  
Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ  
eliminated when the bus switches from read to write, or  
writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ  
high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ  
into a single monolithic circuit.  
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ  
ꢀ
data and control  
•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-  
ing MODE input  
Allsynchronousinputspassthroughregistersarecontrolled  
byꢀaꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.ꢀOperationsꢀ  
may be suspended and all synchronous inputs ignored  
when Clock Enable, CKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ  
device will hold their previous values.  
•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ  
and address pipelining  
•ꢀ PowerꢀDownꢀmode  
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs  
•ꢀ CKE pin to enable clock and suspend operation  
•ꢀ JEDECꢀ100-pinꢀTQFPꢀandꢀ165-ballꢀpackages  
AllꢀRead,ꢀWriteꢀandꢀDeselectꢀcyclesꢀareꢀinitiatedꢀbyꢀtheꢀADVꢀ  
input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ  
isꢀincremented.ꢀNewꢀexternalꢀaddressesꢀcanꢀbeꢀloadedꢀ  
whenꢀADVꢀisꢀLOW.  
•ꢀ Powerꢀsupply:  
Writeꢀ cyclesꢀ areꢀ internallyꢀ self-timedꢀ andꢀ areꢀ initiatedꢀ  
by the rising edge of the clock inputs and when WE is  
LOW.ꢀSeparateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀ  
written.  
NVF:ꢀVd d 2.5Vꢀ(±ꢀ5%),ꢀVd d q ꢀ2.5Vꢀ(±ꢀ5%)  
NLF:ꢀVd d ꢀ3.3Vꢀ(±ꢀ5%),ꢀVd d q ꢀ3.3V/2.5Vꢀ(±ꢀ5%)  
•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀPBGAꢀpackages  
•ꢀ Industrialꢀtemperatureꢀavailable  
•ꢀ Lead-freeꢀavailable  
ꢀAꢀburstꢀmodeꢀpinꢀ(MODE)ꢀdefinesꢀtheꢀorderꢀofꢀtheꢀburstꢀ  
sequence.ꢀWhenꢀtiedꢀHIGH,ꢀtheꢀinterleavedꢀburstꢀsequenceꢀ  
isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ  
selected.  
FAST ACCESS TIME  
Symbol  
Parameter  
6.5  
7.5  
Units  
ns  
tk q ꢀ  
tk c ꢀ  
ꢀ
ClockꢀAccessꢀTimeꢀ  
CycleꢀTimeꢀ  
6.5ꢀ  
7.5ꢀ  
133ꢀ  
7.5ꢀ  
8.5ꢀ  
117ꢀ  
ns  
ꢀ
Frequencyꢀ  
MHz  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
1
Rev. B  
06/09/08  
1234567...23

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与IS61NLF204818A-7.5B3相关器件

型号 品牌 获取价格 描述 数据表
IS61NLF204818A-7.5B3I ISSI

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 		STATE BUS SRAM
IS61NLF204818A-7.5TQ ISSI

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IS61NLF204818A-7.5TQI ISSI

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 		STATE BUS SRAM
IS61NLF204818A-7.5TQLI ISSI

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 		ZBT SRAM, 2MX18, 7.5ns, CMOS, PQFP100, TQFP-100
IS61NLF204836B ISSI

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 		100 percent bus utilization
IS61NLF25618 ISSI

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 		128K*32,128K*36 AND 256K*18 FLOW-THROUGH 'NO WAIT' STATE BUS SRAM
IS61NLF25618-10B ISSI

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 		128K x 32, 128K x 36 and 256K x 18 FLOW-THROUGH NO WAIT STATE BUS SRAM
IS61NLF25618-10BI ISSI

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 		ZBT SRAM, 256KX18, 10ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61NLF25618-10TQ ISSI

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 		128K x 32, 128K x 36 and 256K x 18 FLOW-THROUGH NO WAIT STATE BUS SRAM
IS61NLF25618-8.5B ISSI

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 		128K x 32, 128K x 36 and 256K x 18 FLOW-THROUGH NO WAIT STATE BUS SRAM

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