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IS46R16320E-6BLA1 PDF预览

IS46R16320E-6BLA1

更新时间： 2024-11-19 22:57:35
品牌 Logo 应用领域
美国芯成 - ISSI 动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
34页 770K
描述
IC DRAM 512M PARALLEL 166MHZ

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中文翻译

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IS46R16320E-6BLA1 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TBGA,Reach Compliance Code：compliant
Factory Lead Time：10 weeks风险等级：5.67
访问模式：FOUR BANK PAGE BURST最长访问时间：0.7 ns
其他特性：PROGRAMMABLE CAS LATENCY; AUTO/SELF REFRESHJESD-30 代码：R-PBGA-B60
长度：13 mm内存密度：536870912 bit
内存集成电路类型：DDR DRAM内存宽度：16
功能数量：1端口数量：1
端子数量：60字数：33554432 words
字数代码：32000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：32MX16封装主体材料：PLASTIC/EPOXY
封装代码：TBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE峰值回流温度（摄氏度）：NOT SPECIFIED
座面最大高度：1.2 mm自我刷新：YES
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：8 mmBase Number Matches：1

IS46R16320E-6BLA1 数据手册

 浏览型号IS46R16320E-6BLA1的Datasheet PDF文件第2页浏览型号IS46R16320E-6BLA1的Datasheet PDF文件第3页浏览型号IS46R16320E-6BLA1的Datasheet PDF文件第4页浏览型号IS46R16320E-6BLA1的Datasheet PDF文件第5页浏览型号IS46R16320E-6BLA1的Datasheet PDF文件第6页浏览型号IS46R16320E-6BLA1的Datasheet PDF文件第7页 
IS43R86400E  
IS43/46R16320E, IS43/46R32160E  
16Mx32, 32Mx16, 64Mx8  
512Mb DDR SDRAM  
JANUARY 2020  
FEATURES  
DEVICE OVERVIEW  
• VDD and VDDQ: 2.5V 0.2V ꢀ(5ꢁ (-6  
• VDD and VDDQ: 2.5V 0.1V ꢀ(ꢂ6  
• SSTL_2 compatible I/O  
• Double(data rate architecture; two data transfers  
per clock cycle  
• Bidirectionalꢁ data strobe ꢀDQS6 is transmitted/  
received with dataꢁ to be used in capturing data  
at the receiver  
• DQS is edge(aligned with data for READs and  
centre(aligned with data for WRITEs  
ISSI’s 512(Mbit DDR SDRAM achieves high speed data  
transfer using pipeline architecture and two data word  
accesses per clock cycle. The 53-ꢁ870ꢁ912(bit memory  
array is internally organized as four banks of 128Mb to  
allow concurrent operations. The pipeline allows Read  
and Write burst accesses to be virtually continuousꢁ with  
the option to concatenate or truncate the bursts. The  
programmable features of burst lengthꢁ burst sequence  
and CAS latency enable further advantages. The device  
is available in 8(bitꢁ 1-(bit and 32(bit data word size  
Input data is registered on the I/O pins on both edges  
of Data Strobe signalꢀs6ꢁ while output data is referenced  
to both edges of Data Strobe and both edges of CLK.  
Commands are registered on the positive edges of CLK.  
• Differential clock inputs ꢀCK and CK6  
• DLL aligns DQ and DQS transitions with CK  
transitions  
• Commands entered on each positive CK edge;  
data and data mask referenced to both edges of  
DQS  
An Auto Refresh mode is providedꢁ along with a Self  
Refresh mode. All I/Os are SSTL_2 compatible.  
ADDRESS TABLE  
• Four internal banks for concurrent operation  
• Data Mask for write data. DM masks write data  
at both rising and falling edges of data strobe  
• Burst Length: 2ꢁ ꢂ and 8  
Parameter  
16M x 32  
32M x 16  
64M x 8  
Configuration  
ꢂM x 32 x ꢂ  
banks  
8M x 1- x ꢂ  
banks  
1-M x 8 x ꢂ  
banks  
• Burst Type: Sequential and Interleave mode  
• Programmable CAS latency: 2ꢁ 2.5 and 3  
• Auto Refresh and Self Refresh Modes  
• Concurrent Auto Precharge Supported  
• TRAS Lockout supported ꢀtRAP = tRCD6  
Bank Address Pins  
BA0ꢁ BA1  
BA0ꢁ BA1  
A10/AP  
BA0ꢁ BA1  
A10/AP  
Autoprecharge Pins A8/AP  
Row Address  
8KꢀA0 – A126 8KꢀA0 – A126 8KꢀA0 – A126  
Column Address  
512ꢀA0 – A7ꢁ 1KꢀA0 – A96  
A96  
2KꢀA0 – A9ꢁ  
A116  
Refresh Count  
Com./Ind./A1  
A2  
OPTIONS  
8K / -ꢂms  
8K / 1-ms  
8K / -ꢂms  
8K / 1-ms  
8K / -ꢂms  
8K / 1-ms  
• Configurationꢀs6: 1-Mx32ꢁ 32Mx1-ꢁ -ꢂMx8  
• Packageꢀs6:  
1ꢂꢂ Ball BGA ꢀx326  
--(pin TSOP(II ꢀx8ꢁ x1-6 and -0 Ball BGA ꢀx8ꢁ x1-6  
• Lead(free package  
KEY TIMING PARAMETERS  
Speed Grade  
-4  
-5  
-6  
Units  
x8, x16  
• Temperature Range:  
only  
Commercial ꢀ0°C to +70°C6  
Industrial ꢀ(ꢂ0°C to +85°C6  
Automotiveꢁ A1 ꢀ(ꢂ0°C to +85°C6  
Automotiveꢁ A2 ꢀ(ꢂ0°C to +105°C6  
FCk Max CL = 3  
FCk Max CL = 2.5  
FCk Max CL = 2  
250  
1-7  
133  
200  
1-7  
133  
1-7  
1-7  
133  
MHz  
MHz  
MHz  
Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without  
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest  
version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-  
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications  
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.  
1
Rev. B  
01/13/2020  
1234567...34

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与IS46R16320E-6BLA1相关器件

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IS46R16320E-6BLA2 ISSI

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 		IC DRAM 512M PARALLEL 166MHZ
IS46R16320E-6BLA2-TR ISSI

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 		IC DRAM 512M PARALLEL 166MHZ
IS46R16320E-6TLA1 ISSI

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 		IC DRAM 512M PARALLEL 166MHZ
IS46R16320E-6TLA1-TR ISSI

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 		IC DRAM 512M PARALLEL 166MHZ
IS46R16320E-6TLA2 ISSI

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 		IC DRAM 512M PARALLEL 166MHZ
IS46R16320E-6TLA2-TR ISSI

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 		IC DRAM 512M PARALLEL 166MHZ
IS46R32160D-6BLA1 ISSI

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 		DDR DRAM, 16MX32, 0.7ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MO-205, LFBG
IS46R32160D-6BLA1-TR ISSI

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 		Cache DRAM Module, 16MX32, 0.7ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MO-
IS46R32160D-6BLA2 ISSI

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 		DDR DRAM, 16MX32, 0.7ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, MO-205, LFBGA-144
IS46R32160D-6BLA2-TR ISSI

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 		DDR DRAM, 16MX32, 0.7ns, CMOS, PBGA144,

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