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IS43R32800-5BL PDF预览

IS43R32800-5BL

更新时间: 2024-11-26 01:11:51
品牌 Logo 应用领域
美国芯成 - ISSI 时钟动态存储器内存集成电路
页数 文件大小 规格书
39页 546K
描述
Auto refresh and Self refresh

IS43R32800-5BL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:LFBGA, BGA144,12X12,32针数:144
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.24风险等级:5.52
访问模式:FOUR BANK PAGE BURST最长访问时间:0.7 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):200 MHz
I/O 类型:COMMON交错的突发长度:2,4,8
JESD-30 代码:S-PBGA-B144JESD-609代码:e1
长度:12 mm内存密度:268435456 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:32
湿度敏感等级:3功能数量:1
端口数量:1端子数量:144
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8MX32
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA144,12X12,32
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:2.5 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.4 mm自我刷新:YES
连续突发长度:2,4,8最大待机电流:0.04 A
子类别:DRAMs最大压摆率:0.4 mA
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:12 mm
Base Number Matches:1

IS43R32800-5BL 数据手册

 浏览型号IS43R32800-5BL的Datasheet PDF文件第2页浏览型号IS43R32800-5BL的Datasheet PDF文件第3页浏览型号IS43R32800-5BL的Datasheet PDF文件第4页浏览型号IS43R32800-5BL的Datasheet PDF文件第5页浏览型号IS43R32800-5BL的Datasheet PDF文件第6页浏览型号IS43R32800-5BL的Datasheet PDF文件第7页 
IS43R32800  
8Mx32  
FEBUARY 2009  
256Mb DDR Synchronous DRAM  
FEATURES  
DESCRIPTION:  
IS43R32800 is a 4-bank x 2,097,152-word x32bit  
Double Data Rate Synchronous DRAM, with SSTL_2  
interface. All control and address signals are referenced  
to the rising edge of CLK. Input data is registered on  
both edges of data strobe, and output data and data  
strobe are referenced on both edges of CLK. The  
IS43R32800 achieves very high speed clock rate up to  
200 MHz . It is packaged in 144-ball FBGA.  
•ꢀ Vd d /Vd d q =2.5V+0.2V (-5, -6, -75)  
•ꢀ Double data rate architecture; two data transfers  
per clock cycle  
•ꢀ Bidirectional, data strobe (DQS) is transmitted/  
received with data  
•ꢀ Differential clock input (CLK and /CLK)  
•ꢀ DLL aligns DQ and DQS transitions with CLK  
transitions edges of DQS  
•ꢀ Commands entered on each positive CLK edge;  
•ꢀ Data and data mask referenced to both edges of  
KEY TIMING PARAMETERS  
DQS  
Parameter  
-5  
-6  
-75 Unit  
•ꢀ 4 bank operation controlled by BA0, BA1 (Bank  
Clk Cycle Time  
Address)  
CAS Latency = 3  
CAS Latency = 2.5  
CAS Latency = 2  
5
5
7.5  
6
6
7.5  
7.5  
7.5  
7.5  
ns  
ns  
ns  
•ꢀ /CAS latency –2.0/2.5/3.0 (programmable)  
•ꢀ Burst length - 2/4/8 (programmable)  
•ꢀ Burst type - Sequential/ Interleave (program-  
Clk Frequency  
mable)  
CAS Latency = 3  
CAS Latency = 2.5  
CAS Latency = 2  
200  
200  
143  
167  
167  
143  
143 MHz  
143 MHz  
143 MHz  
•ꢀ Auto precharge / All bank precharge controlled  
by A8  
Access Time from Clock  
CAS Latency = 3  
•ꢀ 4096 refresh cycles/ 64ms (4 banks concurrent  
+0.70 +0.70 +0.70 ns  
refresh)  
CAS Latency = 2.5 +0.70 +0.70 +0.70 ns  
CAS Latency = 2 +0.75 +0.75 +0.70 ns  
•ꢀ Auto refresh and Self refresh  
•ꢀ Row address A0-11/ Column address A0-7, A9-  
SSTL_2 Interface  
•ꢀ Package 144-ball FBGA  
•ꢀ Available in Industrial Temperature  
•ꢀ Temperature Range:  
Commercial (0oC to +70oC)  
ADDRESS TABLE  
Parameter  
8M x 32  
Configuration  
2M x 32 x 4 banks  
BA0, BA1  
Bank Address Pins  
Autoprecharge Pins  
Row Addresses  
Column Addresses  
Refresh Count  
A8/AP  
A0 – A11  
A0 – A7, A9  
4096 / 64ms  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without  
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-  
est version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. A  
01/14/09  

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