PD - 97395E
IRF6718L2TRPbF
IRF6718L2TR1PbF
DirectFET® Power MOSFET
l RoHS Compliant Containing No Lead and Bromide
l Dual Sided Cooling Compatible
Typical values (unless otherwise specified)
VDSS
VGS
RDS(on)
RDS(on)
l Ultra Low Package Inductance
25V max ±20V max
0.50mΩ@10V 1.0mΩ@4.5V
l Very Low RDS(ON) for Reduced Conduction Losses
l Optimized for Active O-Ring / Efuse Applications
l Compatible with existing Surface Mount Techniques
Qg tot Qgd
Qgs2
Qrr
Qoss Vgs(th)
64nC
20nC
9.4nC
67nC
50nC
1.9V
DirectFET® ISOMETRIC
L6
Applicable DirectFET Outline and Substrate Outline
S1
S2
SB
M2
M4
L4
L6
L8
Description
The IRF6718L2TRPbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFET® packaging to achieve
the lowest on-state resistance in a package that has the footprint of a D-pak. The DirectFET package is compatible with existing layout
geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques, when
application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual sided cooling
to maximize thermal transfer in power systems.
The IRF6718L2TRPbF has extremely low Si Rdson coupled with ultra low package resistance to minimize conduction losses. The
IRF6718L2TRPbF has been optimized for parameters that are critical in reliable operation on Active O-Ring / Efuse / hot swap applications.
Absolute Maximum Ratings
Max.
25
Parameter
Units
V
VDS
Drain-to-Source Voltage
±20
61
V
Gate-to-Source Voltage
GS
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
I
I
I
I
@ TA = 25°C
D
D
D
52
A
@ TA = 70°C
@ TC = 25°C
270
490
530
49
DM
EAS
IAR
Single Pulse Avalanche Energy
Avalanche Current
mJ
A
4
3
2
1
0
14.0
12.0
10.0
8.0
I
= 61A
I = 49A
D
D
V
V
= 20V
DS
DS
= 13V
6.0
T
= 125°C
J
4.0
2.0
T
= 25°C
4
J
0.0
2
6
8
10
0
20 40 60 80 100 120 140 160 180
Total Gate Charge (nC)
Q
G
V
Gate -to -Source Voltage (V)
GS,
Fig 1. Typical On-Resistance vs. Gate Voltage
Fig 2. Typical Total Gate Charge vs Gate-to-Source Voltage
Notes:
TC measured with thermocouple mounted to top (Drain) of part.
ꢀ Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 0.44mH, RG = 25Ω, IAS = 49A.
Click on this section to link to the appropriate technical paper.
Click on this section to link to the DirectFET Website.
Surface mounted on 1 in. square Cu board, steady state.
www.irf.com
1
07/27/11