Datasheet > IP-ED8B10B

IP-ED8B10B

更新时间： 2024-11-17 23:58:47

品牌	Logo	应用领域
其他 - ETC		电信数据通信
页数	文件大小	规格书
11页	497K
描述
Telecomm/Datacomm

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IP-ED8B10B 数据手册

8b10b Encoder/Decoder

MegaCore Function

(ED8B10B)

November 2001; ver. 1.02

Data Sheet

Encoders and decoders are used for physical layer coding for Gigabit

Ethernet, Fibre Channel, and other applications. The 8b/10b encoder

takes byte inputs, and generates a direct current (DC) balanced stream

(equal number of 1s and 0s) with a maximum run length of 5. Some of the

individual 10-bit codes will have an equal number of 1s and 0s, while

others will have either four 1s and six 0s, or, six 1s and four 0s. In the latter

case, the disparity between 1s and 0s is used as an input to the next 10-bit

code generation, so that the disparity can be reversed, and maintain an

overall balanced stream. For this reason, some 8-bit inputs have two valid

10-bit codes, depending on the input disparity.

Introduction

The Altera^®8b10b Encoder/Decoder MegaCore^®Function (ED8B10B) is a

compact, high performance core capable of encoding and decoding at

Gigabit Ethernet rates (125 MHz: 1 Gbps). The ED8B10B is optimized for

the APEX^TM20K, FLEX 10K^®, and Mercury^TMdevices.

Look-up table (LUT)-based implementation of encoder

Industry compatible special character coding

Complies with all applicable standards, including:

Features

–

Institute of Electrical and Electronics Engineers, IEEE 802.3z,

Media Access Control (MAC) Parameters, Physical Layer, Repeater

and Management Parameters for 1000 Mb/s Operation, 1998,

paragraphs 36.2.4.1 to 36.2.4.6.

Quartus^®II software, and OpenCore^®feature allow place-and-route

and static timing analysis of designs prior to licensing

Secure register transfer level (RTL) simulation models allow

simulation with user design in third-party simulators

The ED8B10B can encode one 8-bit byte of data into a 10-bit transmission

code, and decode a 10-bit code into one 8-bit byte of data. Figure 1

illustrates the bidirectional conversion process.

Functional

Description

The eight input bits are named A, B, C, D, E, F, G, H. Bit Ais the least

significant bit (LSB), and bit His the most significant bit (MSB). They are

split into two groups: The five-bit group A, B, C, D, E, and the three-bit

group F, G, H.

The coded bits are named a, b, c, d, e, i, f, g, h, j(the order is not

alphabetical). These bits are also split into two groups: the six-bit group a,

b, c, d, e, i, and the four-bit group f, g, h, j.

Altera Corporation

A-DS-IPED8B10B-1.02

12 3 4 5 6 7...11

中文翻译

下载PDF

与IP-ED8B10B相关器件

型号	品牌	获取价格	描述	数据表
IPF009N04NF2S	INFINEON	获取价格	Infineon's StrongIRFET™ 2 power MOSFET 40 V f
IPF010N04NF2S	INFINEON	获取价格	Infineon's StrongIRFET™ 2 power MOSFET 40 V f
IPF010N06NF2S	INFINEON	获取价格	Infineon's StrongIRFET™ 2 power MOSFET 60 V f
IPF012N06NF2S	INFINEON	获取价格	Infineon's StrongIRFET™ 2 power MOSFET 60 V f
IPF013N04NF2S	INFINEON	获取价格	Infineon's StrongIRFET™ 2 power MOSFET 40 V f
IPF014N08NF2S	INFINEON	获取价格	Infineon's StrongIRFET™ 2 power MOSFET 80 V f
IPF015N10N5	INFINEON	获取价格	The IPF015N10N5 is Infineon’s OptiMOS™ 5 powe
IPF016N06NF2S	INFINEON	获取价格	Infineon's StrongIRFET? 2 power MOSFET 60 V features low RDS(on) of 1.65 mOhm, addressing
IPF016N10NF2S	INFINEON	获取价格	Infineon's StrongIRFET™ 2 power MOSFET 100 V
IPF017N08NF2S	INFINEON	获取价格	Infineon's StrongIRFET™ 2 power MOSFET 80 V f

与IP-ED8B10B相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

18
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

12
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

43
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

38

产品中心

服务支持

精选活动

关于我们

帮助中心

IP-ED8B10B

IP-ED8B10B 数据手册

与IP-ED8B10B相关器件

与IP-ED8B10B相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IP-ED8B10B

IP-ED8B10B 数据手册

与IP-ED8B10B相关器件

与IP-ED8B10B相关文章

您还可以找

您在本页遇到什么问题？