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IDTCSPT857DVFQFPN PDF预览

IDTCSPT857DVFQFPN

更新时间: 2024-11-14 23:14:43
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器动态存储器
页数 文件大小 规格书
15页 138K
描述
2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

IDTCSPT857DVFQFPN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
Base Number Matches:1

IDTCSPT857DVFQFPN 数据手册

 浏览型号IDTCSPT857DVFQFPN的Datasheet PDF文件第2页浏览型号IDTCSPT857DVFQFPN的Datasheet PDF文件第3页浏览型号IDTCSPT857DVFQFPN的Datasheet PDF文件第4页浏览型号IDTCSPT857DVFQFPN的Datasheet PDF文件第5页浏览型号IDTCSPT857DVFQFPN的Datasheet PDF文件第6页浏览型号IDTCSPT857DVFQFPN的Datasheet PDF文件第7页 
2.5V - 2.6V PHASE LOCKED  
LOOP DIFFERENTIAL 1:10  
SDRAM CLOCK DRIVER  
IDTCSPT857D  
FEATURES:  
DESCRIPTION:  
• 1 to 10 differential clock distribution  
• Optimized for clock distribution in DDR (Double Data Rate)  
SDRAM applications requiring improved output crosspoint  
voltage  
TheCSPT857DisaPLLbasedclockdriverthatactsasazerodelaybuffer  
todistributeonedifferentialclockinputpair(CLK,CLK)to10differentialoutput  
pairs(Y[0:9],Y[0:9])andonedifferentialpairoffeedbackclockoutput(FBOUT,  
FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the  
outputs to the input reference is provided. A CMOS Enable/Disable pin is  
available for low power disable. When the input frequency falls below  
approximately20MHz,thedevicewillenterpowerdownmode. Inthismode,  
thereceiversaredisabled,thePLListurnedoff,andtheoutputclockdrivers  
aretristated,resultinginacurrentconsumptionoflessthan200µA.  
TheCSPT857Drequiresnoexternalcomponentsandhasbeenoptimised  
forverylowI/Ophaseerror,skew,andjitter,whilemaintainingfrequencyand  
duty cycleovertheoperatingvoltageandtemperaturerange.TheCSPT857D,  
designedforuseinbothmoduleassembliesandsystemmotherboardbased  
solutions,providesanoptimumhigh-performanceclocksource.  
• Operating frequency: 60MHz to 220MHz  
• Very low skew:  
– <100ps for PC1600 - PC2700  
– <75ps for PC3200  
• Very low jitter:  
– <75ps for PC1600 - PC2700  
– <50ps for PC3200  
• 2.5V AVDD and 2.5V VDDQ for PC1600-PC2700  
• 2.6V AVDD and 2.6V VDDQ for PC3200  
• CMOS control signal input  
• Test mode enables buffers while disabling PLL  
• Low current power-down mode  
• Tolerant of Spread Spectrum input clock  
• Available in 48-pin TSSOP and TVSOP, 40-pin VFQFPN, and 56-  
pin VFBGA packages  
The CSPT857D is available in Commercial Temperature Range (0°C to  
+70°C)andIndustrialTemperatureRange(-40°Cto+85°C). SeeOrdering  
Informationfordetails.  
APPLICATIONS:  
• Meets or exceeds JEDEC standard JESD 82-1A for registered  
DDR clock driver  
• Meets proposed DDR1-400 specification  
• For all DDR1 speeds: PC1600 (DDR200), PC2100 (DDR266),  
PC2700 (DDR333), PC3200 (DDR400)  
• Along with SSTV16857, SSTVF16857, SSTV16859, SSTVM16859,  
SSTVF16859, SSTVN16859, DDR1 register, provides complete  
solution for DDR1 DIMMs  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
OCTOBER 2003  
1
c
2003 Integrated Device Technology, Inc.  
DSC-6835/3  

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