IDTCSPUA877A

更新时间： 2024-11-15 04:22:59

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器动态存储器
页数	文件大小	规格书
14页	116K
描述
1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

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IDTCSPUA877A 数据手册

IDTCSPUA877A

1.8VPLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER

COMMERCIALTEMPERATURERANGE

1.8V PHASE LOCKED LOOP

IDTCSPUA877A

DIFFERENTIAL 1:10 SDRAM

CLOCK DRIVER

FEATURES:

DESCRIPTION:

• 1 to 10 differential clock distribution

• Optimized for clock distribution in DDR2 (Double Data Rate)

SDRAM applications

TheCSPUA877AisaPLLbasedclockdriverthatactsasazerodelaybuffer

to distribute one differential clock input pair(CLK, CLK ) to 10 differential

output pairs (Y[0:9], Y[0:9]) and one differential pair of feedback clock output

(FBOUT,FBOUT). Externalfeedbackpins(FBIN,FBIN)forsynchronization

oftheoutputstotheinputreferenceisprovided.OE,OS,andAVDD controlthe

power-downandtestmodelogic. WhenAVDD isgrounded,thePLListurned

offandbypassedfortestmodepurposes. Whenthedifferentialclockinputs

(CLK,CLK)arebothatlogiclow,thisdevicewillenteralowpower-downmode.

Inthismode,thereceiversaredisabled,thePLListurnedoff,andtheoutput

clockdriversaredisabled,resultinginaclockdrivercurrentconsumptionofless

than500μA.

• Operating frequency: 125MHz to 410MHz

• Stabilization time: <6us

• Very low skew: ≤40ps

• Very low jitter: ≤40ps

• 1.8V AV^DDand 1.8V VDDQ

• CMOS control signal input

• Test mode enables buffers while disabling PLL

• Low current power-down mode

• Tolerant of Spread Spectrum input clock

• Available in 52-Ball VFBGA and 40-pin VFQFPN packages

TheCSPUA877Arequiresnoexternalcomponentsandhasbeenoptimised

forverylowphaseerror,skew,andjitter,whilemaintainingfrequencyandduty

cycle over the operating voltage and temperature range. The CSPUA877 ,

designedforuseinbothmoduleassembliesandsystemmotherboardbased

solutions,providesanoptimumhigh-performanceclocksource.

APPLICATIONS:

• Meets or exceeds JEDEC standard CUA877 for registered DDR2

clock driver

TheCSPUA877AisavailableinCommercialTemperatureRange(0°Cto

+70°C). SeeOrderingInformationfordetails.

• Along with SSTUA32864/66, DDR2 register, provides complete

solution for DDR2 DIMMs

FUNCTIONAL BLOCK DIAGRAM

LD or OE

POWER

DOWN

AND

LD, OS, or OE

PLL BYPASS

TEST

MODE

LOGIC

AV^DD

CLK

10KΩ - 100KΩ

PLL

FBIN

NOTE:

The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK.

FBOUT

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

OCTOBER 2006

2006 Integrated Device Technology, Inc.

DSC 6872/4

12 3 4 5 6 7...14

中文翻译

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与IDTCSPUA877A相关器件

型号	品牌	获取价格	描述	数据表
IDTCSPUA877ABVG	IDT	获取价格	1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPUA877ABVG8	IDT	获取价格	PLL Based Clock Driver, CSPUA877 Series, 10 True Output(s), 0 Inverted Output(s), PBGA52,
IDTCSPUA877ANLG	IDT	获取价格	1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPUA877ANLG8	IDT	获取价格	PLL Based Clock Driver, CSPUA877 Series, 10 True Output(s), 0 Inverted Output(s), PQCC40,
IDTCSPUA877BVG	IDT	获取价格	PLL Based Clock Driver, CSPUA877 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, GR
IDTCSPUA877BVG8	IDT	获取价格	PLL Based Clock Driver, CSPUA877 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, GR
IDTCSPUA877NLG	IDT	获取价格	PLL Based Clock Driver, CSPUA877 Series, 10 True Output(s), 0 Inverted Output(s), PQCC40,
IDTCV104B	IDT	获取价格	CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
IDTCV105EPV	IDT	获取价格	Processor Specific Clock Generator, 200MHz, CMOS, PDSO48, SSOP-48
IDTCV105EPV8	IDT	获取价格	Processor Specific Clock Generator, 200MHz, PDSO48, SSOP-48

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