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IDTCV104B PDF预览

IDTCV104B

更新时间: 2024-11-14 22:50:51
品牌 Logo 应用领域
艾迪悌 - IDT 时钟发生器PC
页数 文件大小 规格书
21页 95K
描述
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS

IDTCV104B 数据手册

 浏览型号IDTCV104B的Datasheet PDF文件第2页浏览型号IDTCV104B的Datasheet PDF文件第3页浏览型号IDTCV104B的Datasheet PDF文件第4页浏览型号IDTCV104B的Datasheet PDF文件第5页浏览型号IDTCV104B的Datasheet PDF文件第6页浏览型号IDTCV104B的Datasheet PDF文件第7页 
CLOCK GENERATOR FOR  
IDTCV104B  
DESKTOP PC PLATFORMS  
PRELIMINARY  
DESCRIPTION:  
FEATURES:  
IDTCV104B isa48pinclockgenerationdevicefordesktopPCplatforms.  
ThischipincorporatesfourPLLstoallowindependentgenerationofCPU,AGP/  
PCI, SRC, and 48MHz clocks. The dedicated PLL for Serial ATA clock  
provides high accuracy frequency. This device also implements Band-gap  
referencedIREF toreducetheimpactofVDD variationondifferentialoutputs,  
whichcanprovidemorerobustsystemperformance.  
• 4 PLL architecture  
• Linear frequency programming  
• Independent frequency programming and SSC control  
• Band-gap circuit for differential output  
• High power-noise rejection ratio  
• 66MHz to 533MHz CPU frequency  
• VCO frequency up to 1.1G  
• Support index block read/write, single cycle index block read  
• Programmable REF, 3V66, PCI, 48MHz I/O drive strength  
• Programmable 3V66 and PCI Skew  
• Available in SSOP package  
StaticPLLfrequencydivideerrorcanbeaslowas36ppm, providinghigh  
accuracyoutputclock. EachCPU,AGP/PCI,SRCclockhasitsownSpread  
Spectrumselection.  
KEYSPECIFICATION:  
• CPU/SRC CLK cycle to cycle jitter < 125ps  
• SATA CLK cycle to cycle jitter < 125ps  
• PCI CLK cycle to cycle jitter < 250ps  
• Static PLL frequency divide error as low as 36ppm  
FUNCTIONALBLOCKDIAGRAM  
PLL1  
SSC  
EasyN  
CPU CLK  
CPU[1:0]  
Output Buffers  
Programming  
X1  
XTAL  
Osc Amp  
IREF  
REF 3.1.0  
X2  
3V66/PCI  
Output Buffers  
PLL2  
SSC  
EasyN  
Programming  
PCI[5:0], PCIF[2:0]  
3V66[3:0]  
SDATA  
SM Bus  
Controller  
SCLK  
SRC CLK  
Output Buffer  
PLL3  
SSC  
SRC  
VTT_PWRGD  
Watch Dog  
Timer  
IREF  
FS[1:0]  
Control  
Logic  
48MHz[1:0]  
SEL24_48#  
48MHz  
Output Buffer  
PLL4  
24 - 48MHz  
RESET#  
OUTPUTTABLE  
CPU (Pair)  
3V66  
3V66/VCH  
PCI  
PCIF  
REF  
48MHz  
24 - 48MHz  
SRC (Pair)  
Reset#  
2
3
1
6
3
3
2
1
1
1
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
SEPTEMBER 2003  
1
© 2003 Integrated Device Technology, Inc.  
DSC-6382/16  

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