IDTCV110LPV

更新时间： 2024-02-02 21:27:29

品牌	Logo	应用领域
艾迪悌 - IDT		PC 时钟
页数	文件大小	规格书
16页	89K
描述
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

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中文翻译

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IDTCV110LPV 数据手册

IDTCV110L

COMMERCIALTEMPERATURERANGE

PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR

PROGRAMMABLE FLEXPC

IDTCV110L

CLOCK FOR P4 PROCESSOR

DESCRIPTION:

FEATURES:

IDTCV110Lisa56pinclockdevice.TheCPUoutputbufferisdesignedto

support up to 400MHz processor. This chip has three PLLs inside for CPU/

SRC/PCI,SATA,and48MHz/DOT96IOclocks. OnededicatedPLLforSerial

ATA clock provides high accuracy frequency. This device also implements

Band-gapreferencedIREF toreducetheimpactofVDD variationondifferential

outputs,whichcanprovidemorerobustsystemperformance.

• One high precision PLL for CPU, SSC, and N programming

• One high precision PLL for SRC/PCI/SATA, SSC, and N

programming

• One high precision PLL for 96MHz/48MHz

• Band-gap circuit for differential outputs

• Support spread spectrum modulation, down spread 0.5%

• Support SMBus block read/write, index read/write

• Selectable output strength for REF

StaticPLLfrequencydivideerrorcanbeaslowas36ppm,worsecase114

ppm,providinghighaccuracyoutputclock. EachCPU/SRC/PCI,SATAclock

has its own Spread Spectrum selection, which allows for isolated changes

insteadofaffecting otherclockgroups.

• Allows for CPU frequency to change to a higher frequency for

maximum system computing power

• Available in SSOP package

OUTPUTS:

• 2*0.7V current –mode differential CPU CLK pair

• 6*0.7V current –mode differential SRC CLK pair, one dedicated

forSATA

• One CPU_ITP/SRC selectable CLK pair

• 9*PCI, 3 free running, 33.3MHz

• 1*96MHz,1*48MHz

KEYSPECIFICATION:

• CPU/SRC CLK cycle to cycle jitter < 85ps

• SATA CLK cycle to cycle jitter < 85ps

• PCI CLK cycle to cycle jitter < 250ps

• Static PLL frequency divide error < 114 ppm

• Static PLL frequency divide error for 48MHz < 5 ppm

• 1*REF

FUNCTIONALBLOCKDIAGRAM

PLL1

SSC

N Programmable

CPU CLK

CPU[1:0]

Output Buffers

Stop Logic

CPU_ITP/SRC7

IREF

XTAL

Osc Amp

REF

ITP_EN

SDATA

SM Bus

Controller

SCLK

SRC CLK

Output Buffer

Stop Logic

SRC[6:1]

PLL2

SSC

N Programmable

PCI[5:0], PCIF[2:0]

IREF

VTT_PWRGD#/PD

Control

Logic

48MHz

DOT96

FSA.B.C

48MHz/96MHz

Output BUffer

PLL3

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL TEMPERATURE RANGE

DECEMBER 2004

IDT CONFIDENTIAL

DSC-6534/5

12 3 4 5 6 7...16

中文翻译

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与IDTCV110LPV相关器件

型号	品牌	获取价格	描述	数据表
IDTCV110LPV8	IDT	获取价格	Processor Specific Clock Generator, 400MHz, PDSO56, SSOP-56
IDTCV110LPVG	IDT	获取价格	PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
IDTCV110LPVG8	IDT	获取价格	Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, SSOP-56
IDTCV110NPV	IDT	获取价格	Processor Specific Clock Generator, 400MHz, PDSO56, SSOP-56
IDTCV110NPVG	IDT	获取价格	Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, SSOP-56
IDTCV110NPVG8	IDT	获取价格	Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, SSOP-56
IDTCV111IPA	IDT	获取价格	Processor Specific Clock Generator, 400MHz, PDSO56, TSSOP-56
IDTCV111IPAG	IDT	获取价格	Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56
IDTCV111IPAG8	IDT	获取价格	Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56
IDTCV115-2	IDT	获取价格	PROGRAMMABLE FLEXPC? CLOCK FOR P4 PROCESSOR

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