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IDTCV115FPVG8 PDF预览

IDTCV115FPVG8

更新时间: 2024-11-15 15:45:51
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
19页 105K
描述
Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, SSOP-56

IDTCV115FPVG8 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:56
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
Is Samacsys:NJESD-30 代码:R-PDSO-G56
JESD-609代码:e3长度:18.415 mm
端子数量:56最高工作温度:70 °C
最低工作温度:最大输出时钟频率:400 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
主时钟/晶体标称频率:14.31818 MHz认证状态:Not Qualified
座面最大高度:2.794 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL宽度:7.5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

IDTCV115FPVG8 数据手册

 浏览型号IDTCV115FPVG8的Datasheet PDF文件第2页浏览型号IDTCV115FPVG8的Datasheet PDF文件第3页浏览型号IDTCV115FPVG8的Datasheet PDF文件第4页浏览型号IDTCV115FPVG8的Datasheet PDF文件第5页浏览型号IDTCV115FPVG8的Datasheet PDF文件第6页浏览型号IDTCV115FPVG8的Datasheet PDF文件第7页 
IDTCV115F  
PROGRAMMABLE FLEXPC™  
CLOCK FOR P4 PROCESSOR  
DESCRIPTION:  
FEATURES:  
IDTCV115F is a 56 pin clock device, complying the latest Intel CK410E  
requirements, for Intel advance P4 processors. The CPU output buffer is  
designedtosupportupto400MHzprocessor. OnededicatedPLLforSerial  
ATAclockprovides highaccuracyfrequency. This device alsoimplements  
Band-gapreferencedIREF toreducetheimpactofVDD variationondifferential  
outputs,whichcanprovidemorerobustsystemperformance.  
• One high precision N and SSC programmable PLL for SRC/PCI  
• One high precision N and SSC programmable PLL for CPU  
• One high precision SSC programmable PLL for SATA  
• One high precision PLL for 96MHz/48MHz  
• Band-gap circuit for differential outputs  
• Support multiple spread spectrum modulation, down and  
center  
EachCPU/SRC/PCI,SATAclockhasitsownSpreadSpectrumselection,  
whichallowsforisolatedchangesinsteadofaffecting otherclockgroups.  
• Support SMBus block read/write, index read/write  
• Selectable output strength for REF, PCI, and USB48MHz  
Available in SSOP package  
KEYSPECIFICATIONS:  
• CPU/SRC CLK cycle to cycle jitter < 85ps  
• SATA CLK cycle to cycle jitter < 85ps  
FUNCTIONALBLOCKDIAGRAM  
SATA PLL  
SCC  
SRC4 - SATA  
SATA/  
Programmable  
PCI[4:0], PCIF[2:0]  
PCI/  
PCIEX PLL  
SCC  
N Programmable  
14.318MHz  
Osc  
PCIE/  
Host/  
SRC[6:5] [3:1]  
CPU2_ITP/  
SRC7  
MUX  
CPU PLL  
SCC  
N Programmable  
CPU[1:0]  
USB48  
48MHz/  
96MHz/  
Fixed PLL  
No SCC  
DOT96  
REF  
OUTPUTTABLE  
CPU  
CPU2_ITP/SRC  
SRC  
SATA  
PCI/PCIF  
REF  
DOT96  
48MHz  
2
1
5
1
8
1
1
1
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
APRIL 2005  
1
© 2005 Integrated Device Technology, Inc.  
DSC - 6758/8  

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