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IDTCV136PAG8 PDF预览

IDTCV136PAG8

更新时间: 2024-11-16 21:08:59
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
19页 105K
描述
Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56

IDTCV136PAG8 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:56
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
JESD-30 代码:R-PDSO-G56JESD-609代码:e3
长度:14 mm端子数量:56
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:400 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH主时钟/晶体标称频率:14.31818 MHz
认证状态:Not Qualified座面最大高度:1.1 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
宽度:6.1 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

IDTCV136PAG8 数据手册

 浏览型号IDTCV136PAG8的Datasheet PDF文件第2页浏览型号IDTCV136PAG8的Datasheet PDF文件第3页浏览型号IDTCV136PAG8的Datasheet PDF文件第4页浏览型号IDTCV136PAG8的Datasheet PDF文件第5页浏览型号IDTCV136PAG8的Datasheet PDF文件第6页浏览型号IDTCV136PAG8的Datasheet PDF文件第7页 
IDTCV136  
PROGRAMMABLE FLEXPC™  
CLOCK FOR ATI RS400  
DESCRIPTION:  
FEATURES:  
IDTCV136isa56pinclockdeviceforIntelP4processors.TheCPUoutput  
buffer is designed to support up to 400MHz processor. This device also  
implementsBand-gapreferencedIREFtoreducetheimpactofVDDvariationon  
differentialoutputs,whichcanprovidemorerobustsystemperformance.  
EachCPU/SRCclockhasitsownSpreadSpectrumselection,whichallows  
forisolatedchangesinsteadofaffecting otherclockgroups.  
• One high precision N and SSC programmable PLL for CPU  
• One high precision N and SSC programmable PLL for SRC[2:1]  
• One high precision N and SSC programmable PLL for SRC[7:3]  
SRC0 (PCI Express) and PCI  
• One high precision PLL for 48MHz  
• Band-gap circuit for differential outputs  
• Support multiple spread spectrum modulation, down and  
center  
• Support SMBus block read/write, index read/write  
• Selectable output strength for REF, PCI, 48MHz  
Available in TSSOP package  
KEYSPECIFICATION:  
• CPU CLK cycle to cycle jitter < 85ps  
• SRC CLK cycle to cycle jitter < 125ps  
FUNCTIONALBLOCKDIAGRAM  
SRC  
SSC  
N Programming  
SRC[7:3], 0  
PCI0  
SRC  
PCI/  
SRC PLL  
SSC  
N Programming  
14.318MHz  
Osc  
SRC/  
SRC[2:1]  
CPU[2:0]  
CLKREQ0#  
CLKREQ1#  
CPU PLL  
SSC  
N Programming  
CPU/HOST  
TURBO1#  
USB48  
48MHz  
Fixed PLL  
No SSC  
48MHz/  
REF[2:0]  
Reset#  
OUTPUTTABLE  
CPU  
CLKREQ  
SRC  
PCI  
TURBO  
USB48  
48MHz  
REF  
RESET#  
3
2
8
1
1
1
1
3
1
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
MAY 2005  
1
© 2005 Integrated Device Technology, Inc.  
DSC - 6733/18  

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