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IDTCV107EPVG PDF预览

IDTCV107EPVG

更新时间: 2024-11-15 15:34:51
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
21页 108K
描述
Processor Specific Clock Generator, 200MHz, PDSO48, SSOP-48

IDTCV107EPVG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.34
JESD-30 代码:R-PDSO-G48JESD-609代码:e3
长度:15.875 mm湿度敏感等级:1
端子数量:48最高工作温度:70 °C
最低工作温度:最大输出时钟频率:200 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260主时钟/晶体标称频率:14.31818 MHz
认证状态:Not Qualified座面最大高度:2.794 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.493 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

IDTCV107EPVG 数据手册

 浏览型号IDTCV107EPVG的Datasheet PDF文件第2页浏览型号IDTCV107EPVG的Datasheet PDF文件第3页浏览型号IDTCV107EPVG的Datasheet PDF文件第4页浏览型号IDTCV107EPVG的Datasheet PDF文件第5页浏览型号IDTCV107EPVG的Datasheet PDF文件第6页浏览型号IDTCV107EPVG的Datasheet PDF文件第7页 
CLOCK GENERATOR FOR  
DESKTOP PC PLATFORMS  
IDTCV107E  
DESCRIPTION:  
FEATURES:  
IDTCV107Eisa48pinclockgenerationdevicefordesktopPCplatforms.  
ThischipincorporatesfourPLLstoallowindependentgenerationofCPU,AGP/  
PCI, SRC, and 48MHz clocks. The dedicated PLL for Serial ATA clock  
provides high accuracy frequency. This device also implements Band-gap  
referencedIREF toreducetheimpactofVDD variationondifferentialoutputs,  
whichcanprovidemorerobustsystemperformance.  
• 4 PLL architecture  
Linear frequency programming  
Independent frequency programming and SSC control  
• Band-gap circuit for differential output  
High power-noise rejection ratio  
• 66MHz to 533MHz CPU frequency  
VCO frequency up to 1.1G  
• Support index block read/write, single cycle index block read  
• Programmable REF, 3V66, PCI, 48MHz I/O drive strength  
• Programmable 3V66 and PCI Skew  
Available in SSOP package  
StaticPLLfrequencydivideerrorcanbeaslowas36ppm,providinghigh  
accuracyoutputclock. EachCPU,AGP/PCI,SRCclockhasitsownSpread  
Spectrumselection.  
KEYSPECIFICATION:  
• CPU/SRC CLK cycle to cycle jitter < 125ps  
• SATA CLK cycle to cycle jitter < 125ps  
• PCI CLK cycle to cycle jitter < 250ps  
• Static PLL frequency divide error as low as 36 ppm  
FUNCTIONALBLOCKDIAGRAM  
PLL1  
SSC  
EasyN  
CPU CLK  
CPU[1:0]  
Output Buffers  
Programming  
X1  
XTAL  
Osc Amp  
IREF  
REF 2.1.0  
X2  
AGP/PCI  
Output Buffers  
PLL2  
SSC  
EasyN  
Programming  
PCI[5:0], PCIF[2:0]  
3V66[3:0]  
SDATA  
SM Bus  
Controller  
SCLK  
SRC CLK  
Output Buffer  
PLL3  
SSC  
SRC  
VTT_PWRGD  
Watch Dog  
Timer  
IREF  
FS[1:0]  
Control  
Logic  
48MHz[1:0]  
SEL24_48#  
48MHz  
Output Buffer  
PLL4  
24 - 48MHz  
RESET#  
OUTPUTTABLE  
CPU (Pair)  
3V66  
3V66/VCH  
PCI  
PCIF  
REF  
48MHz  
24 - 48MHz  
SRC (Pair)  
Reset#  
2
3
1
6
3
3
2
1
1
1
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
JANUARY 2004  
1
© 2004 Integrated Device Technology, Inc.  
DSC-6390/15  

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