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IDTCSPU877ANL PDF预览

IDTCSPU877ANL

更新时间: 2024-11-14 21:54:27
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器动态存储器
页数 文件大小 规格书
13页 139K
描述
1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

IDTCSPU877ANL 数据手册

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1.8V PHASE LOCKED LOOP  
IDTCSPU877A  
DIFFERENTIAL 1:10 SDRAM  
CLOCK DRIVER  
FEATURES:  
DESCRIPTION:  
• 1 to 10 differential clock distribution  
• Optimized for clock distribution in DDR2 (Double Data Rate)  
SDRAM applications  
TheCSPU877AisaPLLbasedclockdriverthatactsasazerodelaybuffer  
to distribute one differential clock input pair(CLK, CLK ) to 10 differential  
output pairs (Y[0:9], Y[0:9]) and one differential pair of feedback clock output  
(FBOUT,FBOUT). Externalfeedbackpins(FBIN,FBIN)forsynchronization  
oftheoutputstotheinputreferenceisprovided.OE,OS,andAVDD controlthe  
power-downandtestmodelogic. WhenAVDD isgrounded,thePLListurned  
offandbypassedfortestmodepurposes. Whenthedifferentialclockinputs  
(CLK,CLK)arebothatlogiclow,thisdevicewillenteralowpower-downmode.  
Inthismode,thereceiversaredisabled,thePLListurnedoff,andtheoutput  
clockdriversaredisabled,resultinginacurrentconsumptiondeviceoflessthan  
500µA.  
• Operating frequency: 125MHz to 270MHz  
• Very low skew: 40ps  
• Very low jitter: 40ps  
• 1.8V AVDD and 1.8V VDDQ  
• CMOS control signal input  
• Test mode enables buffers while disabling PLL  
• Low current power-down mode  
• Tolerant of Spread Spectrum input clock  
• Available in 52-Ball VFBGA and 40-pin MLF packages  
TheCSPU877Arequiresnoexternalcomponentsandhasbeenoptimised  
forverylowphaseerror,skew,andjitter,whilemaintainingfrequencyandduty  
cycle over the operating voltage and temperature range. The CSPU877A,  
designedforuseinbothmoduleassembliesandsystemmotherboardbased  
solutions,providesanoptimumhigh-performanceclocksource.  
The CSPU877A is available in Commercial Temperature Range (0°C to  
+70°C). SeeOrderingInformationfordetails.  
APPLICATIONS:  
• Meets or exceeds JEDEC standard 82.8 for registered DDR2  
clock driver  
• Along with SSTU32864/65/66, DDR2 register, provides complete  
solution for DDR2 DIMMs  
FUNCTIONAL BLOCK DIAGRAM  
LD or OE  
POWER  
DOWN  
AND  
OE  
LD, OS, or OE  
PLL BYPASS  
Y0  
TEST  
MODE  
LOGIC  
LD  
OS  
Y0  
Y1  
AVDD  
Y1  
Y2  
Y2  
Y3  
Y3  
Y4  
Y4  
Y5  
CLK  
CLK  
Y5  
Y6  
10K- 100KΩ  
PLL  
Y6  
Y7  
FBIN  
FBIN  
Y7  
Y8  
Y8  
Y9  
Y9  
NOTE:  
The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK.  
FBOUT  
FBOUT  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL TEMPERATURE RANGE  
JANUARY 2004  
1
c
2004 Integrated Device Technology, Inc.  
DSC-6495/4  

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