IDTCSPU877D

更新时间： 2024-11-15 03:40:43

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器动态存储器
页数	文件大小	规格书
13页	140K
描述
1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IDTCSPU877D 数据手册

IDTCSPU877D

COMMERCIALTEMPERATURERANGE

1.8VPLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER

1.8V PHASE LOCKED LOOP

IDTCSPU877D

DIFFERENTIAL 1:10 SDRAM

CLOCK DRIVER

FEATURES:

DESCRIPTION:

• 1 to 10 differential clock distribution

• Optimized for clock distribution in DDR2 (Double Data Rate)

SDRAM applications

TheCSPU877DisaPLLbasedclockdriverthatactsasazerodelaybuffer

to distribute one differential clock input pair(CLK, CLK ) to 10 differential

output pairs (Y[0:9], Y[0:9]) and one differential pair of feedback clock output

(FBOUT,FBOUT). Externalfeedbackpins(FBIN,FBIN)forsynchronization

oftheoutputstotheinputreferenceisprovided.OE,OS,andAVDD controlthe

power-downandtestmodelogic. WhenAVDD isgrounded,thePLListurned

offandbypassedfortestmodepurposes. Whenthedifferentialclockinputs

(CLK,CLK)arebothatlogiclow,thisdevicewillenteralowpower-downmode.

Inthismode,thereceiversaredisabled,thePLListurnedoff,andtheoutput

clockdriversaredisabled,resultinginacurrentconsumptiondeviceoflessthan

500µA.

• Operating frequency: 125MHz to 340MHz

• Very low skew: ≤40ps

• Very low jitter: ≤40ps

• 1.8V AV^DDand 1.8V VDDQ

• CMOS control signal input

• Test mode enables buffers while disabling PLL

• Low current power-down mode

• Tolerant of Spread Spectrum input clock

• Available in 52-Ball VFBGA and 40-pin MLF packages

TheCSPU877Drequiresnoexternalcomponentsandhasbeenoptimised

forverylowphaseerror,skew,andjitter,whilemaintainingfrequencyandduty

cycle over the operating voltage and temperature range. The CSPU877D,

designedforuseinbothmoduleassembliesandsystemmotherboardbased

solutions,providesanoptimumhigh-performanceclocksource.

The CSPU877D is available in Commercial Temperature Range (0°C to

+70°C). SeeOrderingInformationfordetails.

APPLICATIONS:

• Meets or exceeds JEDEC standard 82.8 for registered DDR2

clock driver

• Along with SSTU32864/65/66, DDR2 register, provides complete

solution for DDR2 DIMMs

FUNCTIONAL BLOCK DIAGRAM

LD or OE

POWER

DOWN

AND

LD, OS, or OE

PLL BYPASS

TEST

MODE

LOGIC

AV^DD

CLK

10KΩ - 100KΩ

PLL

FBIN

NOTE:

The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK.

FBOUT

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

AUGUST 2004

2004 Integrated Device Technology, Inc.

DSC 6575/4

12 3 4 5 6 7...13

中文翻译

下载PDF

与IDTCSPU877D相关器件

型号	品牌	获取价格	描述	数据表
IDTCSPU877DBV	IDT	获取价格	1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPU877DBVG	IDT	获取价格	1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPU877DBVG8	IDT	获取价格	PLL Based Clock Driver, 877 Series, 10 True Output(s), 0 Inverted Output(s), GREEN, VFBGA-
IDTCSPU877DNL	IDT	获取价格	1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPU877DNLG	IDT	获取价格	1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPU877DNLG8	IDT	获取价格	PLL Based Clock Driver, 877 Series, 10 True Output(s), 0 Inverted Output(s), PQCC40, GREEN
IDTCSPU877NL	IDT	获取价格	PLL Based Clock Driver, CSPU877 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQC
IDTCSPU877NL8	IDT	获取价格	PLL Based Clock Driver, CSPU877 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQC
IDTCSPU877NLG	IDT	获取价格	PLL Based Clock Driver, CSPU877 Series, 10 True Output(s), 0 Inverted Output(s), PQCC40, P
IDTCSPUA877A	IDT	获取价格	1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

与IDTCSPU877D相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

11
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

4
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

30
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

13

产品中心

服务支持

精选活动

关于我们

帮助中心

IDTCSPU877D

IDTCSPU877D 数据手册

与IDTCSPU877D相关器件

与IDTCSPU877D相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IDTCSPU877D

IDTCSPU877D 数据手册

与IDTCSPU877D相关器件

与IDTCSPU877D相关文章

您还可以找

您在本页遇到什么问题？