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IDTCSPU877DBV PDF预览

IDTCSPU877DBV

更新时间: 2024-11-15 03:40:43
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器动态存储器
页数 文件大小 规格书
13页 140K
描述
1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

IDTCSPU877DBV 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA, BGA52,6X10,25
针数:52Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.91
系列:877输入调节:DIFFERENTIAL
JESD-30 代码:R-XBGA-B52JESD-609代码:e0
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.009 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:52实输出次数:10
最高工作温度:70 °C最低工作温度:
封装主体材料:UNSPECIFIED封装代码:TFBGA
封装等效代码:BGA52,6X10,25封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):225
电源:1.8 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.04 ns座面最大高度:1.05 mm
子类别:Clock Drivers最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn63Pb37)端子形式:BALL
端子节距:0.65 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:4.5 mm
最小 fmax:340 MHzBase Number Matches:1

IDTCSPU877DBV 数据手册

 浏览型号IDTCSPU877DBV的Datasheet PDF文件第2页浏览型号IDTCSPU877DBV的Datasheet PDF文件第3页浏览型号IDTCSPU877DBV的Datasheet PDF文件第4页浏览型号IDTCSPU877DBV的Datasheet PDF文件第5页浏览型号IDTCSPU877DBV的Datasheet PDF文件第6页浏览型号IDTCSPU877DBV的Datasheet PDF文件第7页 
1.8V PHASE LOCKED LOOP  
IDTCSPU877D  
DIFFERENTIAL 1:10 SDRAM  
CLOCK DRIVER  
FEATURES:  
DESCRIPTION:  
• 1 to 10 differential clock distribution  
• Optimized for clock distribution in DDR2 (Double Data Rate)  
SDRAM applications  
TheCSPU877DisaPLLbasedclockdriverthatactsasazerodelaybuffer  
to distribute one differential clock input pair(CLK, CLK ) to 10 differential  
output pairs (Y[0:9], Y[0:9]) and one differential pair of feedback clock output  
(FBOUT,FBOUT). Externalfeedbackpins(FBIN,FBIN)forsynchronization  
oftheoutputstotheinputreferenceisprovided.OE,OS,andAVDD controlthe  
power-downandtestmodelogic. WhenAVDD isgrounded,thePLListurned  
offandbypassedfortestmodepurposes. Whenthedifferentialclockinputs  
(CLK,CLK)arebothatlogiclow,thisdevicewillenteralowpower-downmode.  
Inthismode,thereceiversaredisabled,thePLListurnedoff,andtheoutput  
clockdriversaredisabled,resultinginacurrentconsumptiondeviceoflessthan  
500µA.  
• Operating frequency: 125MHz to 340MHz  
• Very low skew: 40ps  
• Very low jitter: 40ps  
• 1.8V AVDD and 1.8V VDDQ  
• CMOS control signal input  
• Test mode enables buffers while disabling PLL  
• Low current power-down mode  
• Tolerant of Spread Spectrum input clock  
• Available in 52-Ball VFBGA and 40-pin MLF packages  
TheCSPU877Drequiresnoexternalcomponentsandhasbeenoptimised  
forverylowphaseerror,skew,andjitter,whilemaintainingfrequencyandduty  
cycle over the operating voltage and temperature range. The CSPU877D,  
designedforuseinbothmoduleassembliesandsystemmotherboardbased  
solutions,providesanoptimumhigh-performanceclocksource.  
The CSPU877D is available in Commercial Temperature Range (0°C to  
+70°C). SeeOrderingInformationfordetails.  
APPLICATIONS:  
• Meets or exceeds JEDEC standard 82.8 for registered DDR2  
clock driver  
• Along with SSTU32864/65/66, DDR2 register, provides complete  
solution for DDR2 DIMMs  
FUNCTIONAL BLOCK DIAGRAM  
LD or OE  
POWER  
DOWN  
AND  
OE  
LD, OS, or OE  
PLL BYPASS  
Y0  
TEST  
MODE  
LOGIC  
LD  
OS  
Y0  
Y1  
AVDD  
Y1  
Y2  
Y2  
Y3  
Y3  
Y4  
Y4  
Y5  
CLK  
CLK  
Y5  
Y6  
10K- 100KΩ  
PLL  
Y6  
Y7  
FBIN  
FBIN  
Y7  
Y8  
Y8  
Y9  
Y9  
NOTE:  
The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK.  
FBOUT  
FBOUT  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL TEMPERATURE RANGE  
AUGUST 2004  
1
c
2004 Integrated Device Technology, Inc.  
DSC 6575/4  

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