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IDTCSPT857PA8 PDF预览

IDTCSPT857PA8

更新时间: 2024-11-15 20:07:39
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
12页 128K
描述
PLL Based Clock Driver, CSPT857 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, TSSOP-48

IDTCSPT857PA8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP48,.3,20
针数:48Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.3
系列:CSPT857输入调节:DIFFERENTIAL MUX
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
长度:12.5 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:48实输出次数:10
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.5 V
传播延迟(tpd):4.5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.075 ns座面最大高度:1.1 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.1 mm
最小 fmax:60 MHzBase Number Matches:1

IDTCSPT857PA8 数据手册

 浏览型号IDTCSPT857PA8的Datasheet PDF文件第2页浏览型号IDTCSPT857PA8的Datasheet PDF文件第3页浏览型号IDTCSPT857PA8的Datasheet PDF文件第4页浏览型号IDTCSPT857PA8的Datasheet PDF文件第5页浏览型号IDTCSPT857PA8的Datasheet PDF文件第6页浏览型号IDTCSPT857PA8的Datasheet PDF文件第7页 
2.5V PHASE LOCKED LOOP  
DIFFERENTIAL 1:10 SDRAM  
CLOCK DRIVER  
IDTCSPT857/A  
FEATURES:  
DESCRIPTION:  
• Optimized for clock distribution in DDR (Double Data Rate)  
SDRAM applications  
The CSPT857is a PLLbasedclockdriverthatacts as a zerodelaybuffer  
todistributeonedifferentialclockinputpair(CLK,CLK)to10differentialoutput  
pairs(Y[0:9],Y[0:9])andonedifferentialpairoffeedbackclockoutput(FBOUT,  
FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the  
• Operating frequency: 60MHz to 200MHz  
• Standard speed: PC1600 (DDR200), PC2100 (DDR266)  
• A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333) outputs to the input reference is provided. A CMOS Enable/Disable pin is  
• 1 to 10 differential clock distribution  
Very low skew (<100ps)  
Very low jitter (<75ps)  
• 2.5V AVDD and2.5VVDDQ  
• CMOS control signal input  
Test mode enables buffers while disabling PLL  
Low current power-down mode  
Tolerant of Spread Spectrum input clock  
Available in 48-pin TSSOP and 56-pin VFBGA packages  
available for low power disable. When the output frequency falls below  
approximately20MHz,thedevicewillenterpowerdownmode. Inthismode,  
thereceiversaredisabled,thePLListurnedoff,andtheoutputclockdrivers  
aretristated,resultinginacurrentconsumptiondeviceoflessthan200μA.  
TheCSPT857requires noexternalcomponents andhas beenoptimised  
forverylowI/Ophaseerror,skew,andjitter,whilemaintainingfrequencyand  
duty cycleovertheoperatingvoltageandtemperaturerange.TheCSPT857,  
designedforuseinbothmoduleassembliesandsystemmotherboardbased  
solutions,providesanoptimumhigh-performanceclocksource.  
TheCSPT857isonlyavailableinIndustrialTemperatureRange(-40°Cto  
+85°C),andCSPT857AisonlyavailableinCommercialTemperatureRange  
(0°Cto+70°C). SeeOrderingInformationfordetails.  
FUNCTIONALBLOCKDIAGRAM  
37/E6  
PWRDWN  
TEST  
MODE  
LOGIC  
3/A1  
Y0  
16/G2  
2/A2  
Y0  
AVDD  
5/B2  
Y1  
6/B1  
Y1  
10/D1  
Y2  
9/D2  
Y2  
20/J2  
Y3  
19/J1  
Y3  
22/K1  
Y4  
23/K2  
Y4  
46/A6  
13/F1  
Y5  
CLK  
14/F2  
47/A5  
CLK  
Y5  
PLL  
44/B5  
36/F6  
FBIN  
Y6  
35/F5  
43/B6  
FBIN  
Y6  
39/D6  
Y7  
40/D5  
Y7  
29/J5  
Y8  
30/J6  
Y8  
27/K6  
Y9  
26/K5  
Y9  
32/H6  
FBOUT  
33/H5  
FBOUT  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
OCTOBER 2002  
1
c
2002 Integrated Device Technology, Inc.  
DSC-5172/9  

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