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IDTCSPT857PAI PDF预览

IDTCSPT857PAI

更新时间: 2024-11-14 22:23:11
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器动态存储器
页数 文件大小 规格书
12页 125K
描述
2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

IDTCSPT857PAI 数据手册

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2.5V PHASE LOCKED LOOP  
DIFFERENTIAL 1:10 SDRAM  
CLOCK DRIVER  
IDTCSPT857/A  
FEATURES:  
DESCRIPTION:  
• Optimized for clock distribution in DDR (Double Data Rate)  
SDRAM applications  
The CSPT857 is a PLL based clock driver that acts as a zero delay buffer  
todistributeonedifferentialclockinputpair(CLK,CLK)to10differentialoutput  
pairs(Y[0:9],Y[0:9])andonedifferentialpairoffeedbackclockoutput(FBOUT,  
FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the  
• Operating frequency: 60MHz to 200MHz  
• Standard speed: PC1600 (DDR200), PC2100 (DDR266)  
• A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333) outputs to the input reference is provided. A CMOS Enable/Disable pin is  
• 1 to 10 differential clock distribution  
• Very low skew (<100ps)  
• Very low jitter (<75ps)  
• 2.5V AVDD and 2.5V VDDQ  
• CMOS control signal input  
• Test mode enables buffers while disabling PLL  
• Low current power-down mode  
• Tolerant of Spread Spectrum input clock  
• Available in 48-pin TSSOP and 56-pin VFBGA packages  
available for low power disable. When the output frequency falls below  
approximately20MHz,thedevicewillenterpowerdownmode. Inthismode,  
thereceiversaredisabled,thePLListurnedoff,andtheoutputclockdrivers  
aretristated,resultinginacurrentconsumptiondeviceoflessthan200µA.  
TheCSPT857requiresnoexternalcomponentsandhasbeenoptimised  
forverylowI/Ophaseerror,skew,andjitter,whilemaintainingfrequencyand  
duty cycleovertheoperatingvoltageandtemperaturerange.TheCSPT857,  
designedforuseinbothmoduleassembliesandsystemmotherboardbased  
solutions,providesanoptimumhigh-performanceclocksource.  
TheCSPT857isonlyavailableinIndustrialTemperatureRange(-40°Cto  
+85°C),andCSPT857AisonlyavailableinCommercialTemperatureRange  
(0°Cto+70°C). SeeOrderingInformationfordetails.  
FUNCTIONALBLOCKDIAGRAM  
37/E6  
PWRDWN  
TEST  
MODE  
LOGIC  
3/A1  
Y0  
16/G2  
2/A2  
Y0  
AVDD  
5/B2  
Y1  
6/B1  
Y1  
10/D1  
Y2  
9/D2  
Y2  
20/J2  
Y3  
19/J1  
Y3  
22/K1  
Y4  
23/K2  
Y4  
46/A6  
13/F1  
Y5  
CLK  
14/F2  
47/A5  
CLK  
Y5  
PLL  
44/B5  
36/F6  
FBIN  
Y6  
35/F5  
43/B6  
FBIN  
Y6  
39/D6  
Y7  
40/D5  
Y7  
29/J5  
Y8  
30/J6  
Y8  
27/K6  
Y9  
26/K5  
Y9  
32/H6  
FBOUT  
33/H5  
FBOUT  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
OCTOBER 2002  
1
c
2002 Integrated Device Technology, Inc.  
DSC-5172/8  

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