128K X 36, 3.3V Synchronous
IDT71V547
SRAM with ZBT™ Feature, Burst
Counter and Flow-Through Outputs
Features
◆
128K x 36 memory configuration, flow-through outputs
TheIDT71V547containsaddress,data-inandcontrolsignalregisters.
Theoutputsareflow-through(nooutputdataregister).Outputenableis
theonlyasynchronoussignalandcanbeusedtodisabletheoutputsat
anygiventime.
◆
Supports high performance system speed - 95 MHz
(8ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
◆
cycles
A Clock Enable (CEN) pin allows operation of the IDT71V547 to
be suspended as long as necessary. All synchronous inputs are
ignored when CENis high and the internal device registers will hold
their previous values.
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser
todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive
whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany
burstinprogressisstopped.However,anypendingdatatransfers(reads
orwrites)willbecompleted.Thedatabuswilltri-stateonecycleafterthe
chipwasdeselectedorwriteinitiated.
◆
Internally synchronized signal eliminates the need to
control OE
Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
Single 3.3V power supply (±5%)
Packaged in a JEDEC standard 100-pin TQFP package
◆
◆
◆
◆
◆
◆
TheIDT71V547hasanon-chipburstcounter. Intheburstmode,the
IDT71V547canprovidefourcyclesofdataforasingleaddresspresented
totheSRAM.TheorderoftheburstsequenceisdefinedbytheLBOinput
pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence.
The ADV/LDsignalis usedtoloada newexternaladdress (ADV/LD=
LOW)orincrementtheinternalburstcounter(ADV/LD=HIGH).
TheIDT71V547SRAMutilizesIDT'shigh-performance,high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity.
Description
The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronousSRAMorganizedas128Kx36bits. Itisdesignedtoeliminate
deadbuscycleswhenturningthebusaroundbetweenreadsandwrites,
orwritesandreads.ThusithasbeengiventhenameZBTTM,orZeroBus
Turn-around.
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle,andonthenextclockcycle,itsassociateddatacycleoccurs,beit
read or write.
PinDescriptionSummary
0
16
A - A
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Three Chip Enables
Output Enable
1
2
2
CE , CE , CE
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
1
2
3
4
BW , BW , BW , BW
CLK
ADV/LD
Advance Burst Address / Load New Address
Linear / Interleaved Burst Order
Data Input/Output
3.3V Power
Synchronous
Static
LBO
0
31
P1
I/O - I/O , I/O -
Synchronous
Static
P4
I/O
DD
V
Supply
Supply
SS
V
Ground
Static
3822 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
DECEMBER 1999
1
DSC-3822/03
©1999IntegratedDeviceTechnology,Inc.